TRENCH MOSFET HAVING AN INDEPENDENT COUPLED ELEMENT IN A TRENCH

• US 20160322901A1
• Filed: 07/11/2016
• Published: 11/03/2016
• Est. Priority Date: 09/14/2012
• Status: Active Grant

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Inventors: Sato, Tetsuo, Uno, Tomoaki, Kato, Hirokazu, Matsuura, Nobuyoshi
• Granted Patent: US 10,069,415 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 2017/6878 using multi-gate field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.

Claims

1. An apparatus comprising:

a first transistor comprising;

a first trench formed in a first semiconductor substrate;

a first source;

a first drain;

a first gate;

a first conductive element in the first trench;

wherein the first conductive element extends between the first gate and a bottom of the first trench;

wherein the first conductive element is isolated from the first source and the first gate by an insulating material;

a circuit for generating a first pulse width modulated (PWM) signal at a first output, wherein the first output of the circuit is electrically coupled to the first gate.

2. The apparatus of claim 1 further comprising:

a second transistor comprising;

a second trench formed in a second semiconductor substrate;

a second source;

a second drain;

a second gate;

a second conductive element in the second trench;

wherein the second conductive element extends between the second gate and a bottom of the second trench;

wherein the second conductive element is isolated from the second source and the second gate by an insulating material;

wherein the circuit is configured to generate a second PWM signal at a second output, wherein the second output of the circuit is electrically coupled to the second gate.

3. The apparatus of claim 2 further comprising:

an inductor comprising first and second terminals;

wherein the first source and the second drain are electrically coupled together and to the first terminal of the inductor, and;

wherein the first and second conductive elements are electrically coupled together.

4. The apparatus of claim 3 further comprising:

a resistor comprising first and second terminals;

wherein the first and second conductive elements are electrically coupled to the first and second terminals of the resistor, respectively.

5. The apparatus of claim 1 wherein the first semiconductor substrate comprises a first drain layer, a first drift layer, a first base layer, and a first source layer, wherein the first drift and base layers extend between the first drain and source layers, wherein the first base layer extends between the first source drift layers, wherein the first source and base layers are in ohmic contact with the first source, and wherein the first drain layer is in ohmic contact with the first drain, and wherein the first conductive element extends between the first gate and the first drain layer.

6. The apparatus of claim 5 wherein the first trench extends into the first source, base, and drift layers, but not into the first drain layer, and wherein the first gate is adjacent the first base layer and is configured to influence the conductance thereof.

7. The apparatus of claim 1 wherein a lateral thickness of insulating material between the first gate and the trench is less than a lateral thickness of insulating material between the first conductive element and the trench.

8. The apparatus of claim 7 wherein a distance between opposing sidewalls of the trench adjacent the first gate is greater than a distance between opposing sidewalls of the trench adjacent the first conductive element.

9. The apparatus of claim 7 wherein a cross sectional width of the first gate is greater than a cross sectional width of the first conductive element.

10. The apparatus of claim 1 wherein a length of the first gate is equal to or greater than a length of the first conductive element.

11. The apparatus of claim 1 wherein a width of insulating material between the first gate and the first conductive element is greater than a lateral thickness of insulating material between the first gate and the trench.

12. The apparatus of claim 1 wherein the first transistor comprises a base layer extending between a source layer and a drift layer, wherein the trench extends through each of the source, base, and drift layers, wherein a length of the base layer that extends between the source layer and the drift layer is greater than an extension of the first gate past a boundary between the base layer and the drift layer.

13. The apparatus claim 1 further comprising a first circuit, wherein the first circuit is configured to couple the first conductive element to a first voltage while the first transistor is in an active state.

14. The apparatus of claim 13 wherein the first circuit is configured to couple the first conductive element to a second voltage while the first transistor is in an inactive state, and wherein the first voltage is different than the second voltage.

15. The apparatus of claim 12 wherein the first circuit is configured to decouple the first conductive element from the first voltage as the first transistor transitions from the active state to the inactive state, and wherein the first circuit is configured to couple the first conductive element to the second voltage as the first transistor transitions from the active state to the inactive state.

16. The apparatus of claim 14 wherein the first circuit is configured to decouple the first conductive element from the second voltage as the first transistor transitions from the inactive state to the active state, and wherein the first circuit is configured to couple the first conductive element to the first voltage as the first transistor transitions from the inactive state to the active state.

17. The apparatus of claim 2 wherein the first and second PWM signals are complementary and non-overlapping.

18. The apparatus of claim 1 further comprising:

a second transistor comprising;

a second trench formed in a second semiconductor substrate;

a second source;

a second drain;

a second gate;

a second conductive element in the second trench;

wherein the second conductive element extends between the second gate and a bottom of the second trench;

wherein the second conductive element is isolated from the second source and the second gate by an insulating material;

wherein the first and second drains are electrically coupled to each other;

wherein the circuit is configured to generate a second PWM signal at a second output, wherein the second output of the circuit is electrically coupled to the second gate.

19. The apparatus of claim 18 further comprising

an inductor comprising first and second terminals;

wherein the first and second sources are electrically coupled to the first and second terminals, respectively, of the inductor.

20. The apparatus of claim 19 further comprising:

first and second inductors;

wherein the first and second sources are electrically coupled to the first and second inductors, respectively.