MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE AND PROGRAM METHOD THEREOF

• US 20160329084A1
• Filed: 03/10/2016
• Published: 11/10/2016
• Est. Priority Date: 05/06/2015
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: HAN, Ju Hyeon
• Granted Patent: US 9,564,189 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 16/3486 Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5624 Concurrent multilevel programming and programming verification
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A method of programming a memory system includes: reading a target page included in a selected memory block in response to a program request when at least one of the pages included in the selected memory block contains data; and performing a program for the target page when, among the data bits included in the data read from the target page, the number of data bits having a first logic value is equal to or less than a preset value.

Claims

1. A method of programming a memory system including a semiconductor memory device with a plurality of memory blocks, each memory block comprising a plurality of pages, the method comprising:

reading a target page included in a selected memory block in response to a program request when at least one of the plurality of the pages included in the selected memory block contains data; and

performing a program for the target page when, among data bits included in the data read from the target page, a number of data bits having a first logic value is equal to or less than a preset value.

2. The method according to claim 1, further comprising:

performing the program on a page of a memory block other than the selected memory block when, among data bits included in the read data, the number of data bits having the first logic value is greater than the preset value.

3. The method according to claim 1, further comprising:

performing a partial erase operation for the target page when, among data bits included in the read data, the number of data bits having the first logic value is greater than the preset value; and

performing a program for the target page after the partial erase operation.

4. The method according to claim 1, further comprising:

performing the program for the target page when the pages included in the selected memory block do not contain data.

5. The method according to claim 1,

wherein the pages included in the selected memory block have an erase state and a plurality of program states when storing data, and

wherein the test read voltage falls within a read margin between a voltage range of the erase state and a voltage range of a lowest program state among the plurality of program states.

6. The method according to claim 1, wherein the reading the target page comprises reading the target page included in the selected memory block in response to the program request using a test read voltage.

7. The method according to claim 6, wherein the reading the target page using the test read voltage comprises:

controlling the semiconductor memory device to generate the test read voltage during a read operation; and

controlling the semiconductor memory device to perform the read operation for the target page.

8. The method according to claim 1, further comprising:

receiving the program request; and

defining the target page included in the selected memory block in response to the program request.

9. The method according to claim 8, wherein the defining the target page comprises:

converting a logic block address included in the program request into a physical block address corresponding to the target page with reference to mapping information between logic block addresses and physical block addresses.

10. A memory system comprising:

a semiconductor memory device comprising a plurality of memory blocks, each of which includes a plurality of pages; and

a controller configured so that the controller reads a target page depending on whether at least one of pages of a memory block including the target page contains data,

wherein the controller performs a program for the target page when, among data bits included in the data read from the target page, a number of data bits having a first logic value is equal to or less than a preset value.

11. The memory system according to claim 10, wherein the controller performs the program for the target page when the pages of the memory block including the target page do not contain data.

12. The memory system according to claim 10,

wherein the plurality of pages have an erase state and a plurality of program states when storing data, and

wherein the test read voltage falls within a read margin between a voltage range of the erase state and a voltage range of a lowest program state among the plurality of program states.

13. The memory system according to claim 10, wherein when, among data bits included in the read data, the number of data bits having the first logic value is greater than the preset value, the controller performs the program on a page of a memory block other than the memory block including the target page.

14. The memory system according to claim 10, wherein when, among data bits included in the read data, the number of data bits having the first logic value is greater than the preset value, the controller performs a partial erase operation for the target page and then performs the program for the target page.

15. A memory system comprising:

a semiconductor memory device comprising a plurality of memory blocks, each memory block comprising a plurality of pages; and

a controller suitable for reading a target page depending on whether, among pages of a first memory block including the target page, a number of pages that contain data is equal or greater than a predetermined number,

wherein the controller performs a program for the target page when, among data bits included in the data read from the target page, a number of data bits having a first logic value is equal to or less than a preset value.

16. The memory system according to claim 15, wherein when, among the pages of the first memory block, the number of pages that contain data is less than the predetermined number, the controller performs the program for the target page.

17. The memory system according to claim 15,

wherein the plurality of pages have an erase state and a plurality of program states when storing data, and

wherein the test read voltage falls within a read margin between a voltage range of the erase state and a voltage range of a lowest program state among the plurality of program states.

18. The memory system according to claim 15, wherein the controller performs the program on a page of a second memory block, when, among data bits included in the read data, the number of data bits having the first logic value is greater than the preset value.

19. The memory system according to claim 15, wherein when, among data bits included in the read data, the number of data bits having the first logic value is greater than the preset value, the controller performs a partial erase operation for the target page and then performs the program for the target page.

20. The memory system according to claim 15, wherein the controller reads the target page using a test read voltage by controlling the semiconductor memory device to generate the test read voltage during a read operation and controlling the semiconductor memory device to perform the read operation for the target page.