FAN-OUT PACKAGE STRUCTURE INCLUDING ANTENNA

• US 20160329299A1
• Filed: 04/17/2016
• Published: 11/10/2016
• Est. Priority Date: 05/05/2015
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: LIU, Nai-Wei, LIN, Tzu-Hung, PENG, I-Hsuan, HSIAO, Ching-Wen, HUANG, Wei-Che
• Application Number:
  US15/130,994
• Publication Number:
  US 20160329299A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/1205 Capacitor
• CPC Class Codes: H01L 2924/1206 : Inductor
• CPC Class Codes: H01L 2924/1207 : Resistor
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01L 2924/1435 : Random access memory [RAM]
• CPC Class Codes: H01L 2924/1438 : Flash memory
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.

Claims

1. A semiconductor package structure, comprising:

a first semiconductor package, comprising;

a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto;

a first semiconductor die disposed on the first surface of the first RDL structure;

a first molding compound disposed on the first surface of the first RDL structure and surrounding the first semiconductor die; and

an inter-metal dielectric (IMD) structure disposed on the first molding compound and the first semiconductor die, wherein the IMD structure has a conductive layer with an antenna pattern electrically coupled to the first RDL structure.

2. The semiconductor package structure as claimed in claim 1, wherein the first semiconductor package further comprises an electronic component disposed on the second surface of the first RDL structure and electrically coupled to the first RDL structure.

3. The semiconductor package structure as claimed in claim 2, wherein the electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof.

4. The semiconductor package structure as claimed in claim 1, wherein the first semiconductor package further comprises a plurality of first conductive structures disposed on the second surface of the first RDL structure and electrically coupled to the first RDL structure.

5. The semiconductor package structure as claimed in claim 1, wherein the first semiconductor package further comprises a passivation layer covering the IMD structure.

6. The semiconductor package structure as claimed in claim 1, wherein the first semiconductor package further comprises a second semiconductor die disposed on the first surface of the first RDL structure, such that the first and second semiconductor dies are arranged side-by-side.

7. The semiconductor package structure as claimed in claim 1, wherein the first semiconductor package further comprises a plurality of first vias passing through the first molding compound to form an electrical connection between the first RDL structure and the conductive layer with the antenna pattern.

8. The semiconductor package structure as claimed in claim 7, further comprising:

a second semiconductor package stacked below the first semiconductor package, comprising;

a second RDL structure electrically coupled to the first RDL structure and having a third surface and a fourth surface opposite thereto;

a third semiconductor die disposed between the third surface of the second RDL structure and the second surface of the first RDL structure; and

a second molding compound disposed between the third surface of the second RDL structure and the second surface of the first RDL structure and surrounding the third semiconductor die.

9. The semiconductor package structure as claimed in claim 8, wherein the first semiconductor package further comprises a second semiconductor die disposed on the first surface of the first RDL structure, such that the first and second semiconductor dies are arranged side-by-side.

10. The semiconductor package structure as claimed in claim 9, wherein at least one of the first, second, and third semiconductor dies comprises a microcontroller, a microprocessor, a random access memory, a power management integrated circuit, a flash memory, a global positioning system device, or a radio frequency device.

11. The semiconductor package structure as claimed in claim 8, wherein the second semiconductor package further comprises an electronic component disposed on the fourth surface of the second RDL structure and electrically coupled to the second RDL structure.

12. The semiconductor package structure as claimed in claim 11, wherein the electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof.

13. The semiconductor package structure as claimed in claim 8, wherein the second semiconductor package further comprises a plurality of second conductive structures disposed on the fourth surface of the second RDL structure and electrically coupled to the second RDL structure.

14. The semiconductor package structure as claimed in claim 8, wherein the second semiconductor package further comprises a plurality of second vias passing through the second molding compound to form an electrical connection between the first and second RDL structures.

15. The semiconductor package structure as claimed in claim 14, wherein at least one of the plurality of second vias is vertically aligned with at least one of the plurality of first vias.

16. A semiconductor package structure, comprising:

a first semiconductor package, comprising;

a first RDL structure having a first surface and a second surface opposite thereto;

a first semiconductor die disposed on the first surface of the first RDL structure;

a first molding compound disposed on the first surface of the first RDL structure and surrounding the first semiconductor die; and

an IMD structure disposed on the first molding compound and the first semiconductor die, wherein the IMD structure has a conductive shielding layer covering the first semiconductor die.

17. The semiconductor package structure as claimed in claim 16, wherein the first semiconductor package further comprises an electronic component disposed on the second surface of the first RDL structure and electrically coupled to the first RDL structure.

18. The semiconductor package structure as claimed in claim 17, wherein the electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof.

19. The semiconductor package structure as claimed in claim 16, wherein the first semiconductor package further comprises a plurality of first conductive structures disposed on the second surface of the first RDL structure and electrically coupled to the first RDL structure.

20. The semiconductor package structure as claimed in claim 16, wherein the first semiconductor package further comprises a second semiconductor die disposed on the first surface of the first RDL structure and covered by the conductive shielding layer, such that the first and second semiconductor dies are arranged side-by-side.

21. The semiconductor package structure as claimed in claim 16, wherein the first semiconductor package further comprises a plurality of first vias passing through the first molding compound and electrically coupled to the first RDL structure.

22. The semiconductor package structure as claimed in claim 21, further comprising:

a second semiconductor package stacked below the first semiconductor package, comprising;

a second RDL structure electrically coupled to the first RDL structure and having a third surface and a fourth surface opposite thereto;

a third semiconductor die disposed between the third surface of the second RDL structure and the second surface of the first RDL structure; and

a second molding compound disposed between the third surface of the second RDL structure and the second surface of the first RDL structure and surrounding the third semiconductor die.

23. The semiconductor package structure as claimed in claim 22, wherein the first semiconductor package further comprises a second semiconductor die disposed on the first surface of the first RDL structure and covered by the conductive shielding layer, such that the first and second semiconductor dies are arranged side-by-side.

24. The semiconductor package structure as claimed in claim 23, wherein at least one of the first, second, and third semiconductor dies comprises a microcontroller, a microprocessor, a random access memory, a power management integrated circuit, a flash memory, a global positioning system device, or a radio frequency device.

25. The semiconductor package structure as claimed in claim 22, wherein the second semiconductor package further comprises an electronic component disposed on the fourth surface of the second RDL structure and electrically coupled to the second RDL structure.

26. The semiconductor package structure as claimed in claim 25, wherein the electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof.

27. The semiconductor package structure as claimed in claim 22, wherein the second semiconductor package further comprises a plurality of second conductive structures disposed on the fourth surface of the second RDL structure and electrically coupled to the second RDL structure.

28. The semiconductor package structure as claimed in claim 22, wherein the second semiconductor package further comprises a plurality of second vias passing through the second molding compound to form an electrical connection between the first and second RDL structures.