SUB-FIN DOPED BULK FIN FIELD EFFECT TRANSISTOR (FINFET), INTEGRATED CIRCUIT (IC) AND METHOD OF MANUFACTURE
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Abstract
A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the IC. Fins on pedestals are defined, e.g., with a hard mask, in a fin layer on a semiconductor wafer and spaces between the pedestals are filled with dielectric material, e.g., shallow trench isolation (STI). Sacrificial sidewalls are forming along the sides of fins and pedestal sub-fins sidewalls are re-exposed. Pedestal sub-fins are doped with a punch-though dopant and punch-though dopant is diffused into the sub-fins and the bottoms of fins. After removing the hard mask and sacrificial sidewalls, metal FET gates are formed on the fins.
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Citations
25 Claims
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1-7. -7. (canceled)
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8. A method of forming an integrated circuit (IC) including a plurality of FinFETs, said method comprising:
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forming a fin layer on a wafer, said wafer being a first semiconductor material and said fin layer being a second semiconductor material; defining fins on pedestals on said wafer, said pedestals being formed from an upper surface of said wafer, said fins being defined from said fin layer; forming a dielectric material filling between said pedestals; forming sacrificial sidewalls along sides of said fins; exposing sidewalls of pedestal sub-fins; forming punch-through diffusion regions in said pedestal sub-fins extending into bottoms of said fins; and forming FET gates on said fins. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of forming an integrated circuit (IC) including a plurality of FinFETs, said method comprising:
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forming a fin layer on a wafer, said wafer being a first semiconductor material and said fin layer being a second semiconductor material; defining fins on pedestals on said wafer, said pedestals being formed from an upper surface of said wafer, said fins being defined from said fin layer; forming a dielectric material filling between said pedestals; forming sacrificial sidewalls along sides of said fins; exposing sidewalls of pedestal sub-fins; doping said pedestal sub-fins with a punch-though dopant; diffusing said punch-though dopant into said pedestal sub-fins and bottoms of said fins; and forming metal FET gates on said fins. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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Specification