ACCELERATING ALGORITHMS & APPLICATIONS ON FPGAs

• US 20160335120A1
• Filed: 05/10/2016
• Published: 11/17/2016
• Est. Priority Date: 05/11/2015
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Auviz Systems, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Gupta, Nagesh Chandrasekaran, Santhaseelan, Varun
• Granted Patent: US 11,099,918 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/547 Remote procedure calls [RPC]; Web services

Abstract

A method for accelerating algorithms and applications on field-programmable gate arrays (FPGAs). The method includes: obtaining, from a host application, by a run-time configurable kernel, implemented on an FPGA, a first set of kernel input data; obtaining, from the host application, by the run-time configurable kernel, a first set of kernel operation parameters; parameterizing the run-time configurable kernel at run-time, using the first set of kernel operation parameters; and performing, by the parameterized run-time configurable kernel, a first kernel operation on the first set of kernel input data to obtain a first set of kernel output data.

Claims

1. A method for accelerating algorithms and applications on field-programmable gate arrays (FPGAs), the method comprising:

obtaining, from a host application, by a run-time configurable kernel, implemented on an FPGA, a first set of kernel input data;

obtaining, from the host application, by the run-time configurable kernel, a first set of kernel operation parameters;

parameterizing the run-time configurable kernel at run-time, using the first set of kernel operation parameters; and

performing, by the parameterized run-time configurable kernel, a first kernel operation on the first set of kernel input data to obtain a first set of kernel output data.

2. The method of claim 1, further comprising:

obtaining, from the host application, by the run-time configurable kernel, a second set of kernel operation parameters;

re-parameterizing the run-time configurable kernel, using the second set of kernel operation parameters;

performing, by the re-parameterized run-time configurable kernel, a second kernel operation on a second set of kernel input data to obtain a second set of kernel output data.

3. The method of claim 2, wherein the second set of kernel input data is obtained from the first set of kernel output data.

4. The method of claim 1, further comprising:

obtaining, from the host application, by a second run-time configurable kernel, implemented on the FPGA, a second set of kernel operation parameters;

parameterizing the second run-time configurable kernel at run-time, using the second set of kernel operation parameters; and

performing, by the second parameterized run-time configurable kernel, a second kernel operation on a second set of kernel input data to obtain a second set of kernel output data.

5. The method of claim 1, further comprising, after performing the first kernel operation, retrieving, by the host, the first set of kernel output data from the FPGA.

6. The method of claim 1, wherein the first kernel operation is one selected from the group consisting of a convolutional neural network, a recurrent neural network, a convolution, a de-convolution, a matrix multiplication, and a vector multiplication.

7. The method of claim 1, wherein the kernel operation parameters comprise at least one selected from the group consisting of a dimensionality of the kernel input data, a dimensionality of the kernel output data, a convolution filter kernel, a convolution filter kernel stride, a pooling stride, a pooling window size, a number of input feature maps, a number of output feature maps, and an output feature map size.

8. The method of claim 1,

wherein the first set of kernel input data comprises a plurality of data points;

and

wherein the performing of the first kernel operation on the first set of kernel input data comprises processing the plurality of data points in parallel, by a plurality of processing elements of the run-time configurable kernel.

9. The method of claim 1, further comprising, prior to obtaining the first set of kernel input data by the run-time configurable kernel:

programming the kernel into the FPGA, comprising;

deriving, from a kernel template, an FPGA-specific kernel by scaling the kernel template according to the specifications of the FPGA; and

installing the scaled kernel on the FPGA.

10. The method of claim 1, further comprising:

obtaining, from a second host application, by the run-time configurable kernel, implemented on the FPGA, a second set of kernel input data;

obtaining, from the second host application, by the run-time configurable kernel, a second set of kernel operation parameters;

parameterizing the run-time configurable kernel at run-time, using the second set of kernel operation parameters; and

performing, by the parameterized run-time configurable kernel, a second kernel operation on the second set of kernel input data to obtain a second set of kernel output data.

11. A system for accelerating algorithms and applications on field-programmable gate arrays (FPGAs), comprising:

a host computing device;

an FPGA device; and

a run-time configurable kernel executing on an FPGA of the FPGA device and configured to;

obtain, from a host application executing on the host computing device, a first set of kernel input data;

obtain, from the host application, a first set of kernel operation parameters;

parameterize the run-time configurable kernel at run-time, using the first set of kernel operation parameters; and

perform a first kernel operation on the first set of kernel input data to obtain a first set of kernel output data.

12. The system of claim 11, wherein the run-time configurable kernel is further configured to:

obtain, from the host application, a second set of kernel operation parameters;

re-parameterize the run-time configurable kernel, using the second set of kernel operation parameters; and

perform, after the re-parameterization, a second kernel operation on a second set of kernel input data to obtain a second set of kernel output data.

13. The system of claim 11, wherein the first kernel operation is one selected from the group consisting of a convolutional neural network, a recurrent neural network, a convolution, a de-convolution, a matrix multiplication, and a vector multiplication.

14. The system of claim 11, wherein the kernel operation parameters comprise at least one selected from the group consisting of a dimensionality of the kernel input data, a dimensionality of the kernel output data, a convolution filter kernel, a convolution filter kernel stride, a pooling stride, a pooling window size, a number of input feature maps, a number of output feature maps, and an output feature map size.

15. The system of claim 11, wherein the host computing device and the FPGA device are configured to, prior to obtaining the first set of kernel input data:

program the kernel into the FPGA by;

deriving, from a kernel template, an FPGA-specific kernel by scaling the kernel template according to the specifications of the FPGA; and

installing the scaled kernel on the FPGA.

16. A non-transitory computer readable medium (CRM) storing instructions for accelerating algorithms and applications on field-programmable gate arrays (FPGAs), the instructions comprising functionality for:

obtaining, from a host application, by a run-time configurable kernel, implemented on an FPGA, a first set of kernel input data;

obtaining, from the host application, by the run-time configurable kernel, a first set of kernel operation parameters;

parameterizing the run-time configurable kernel at run-time, using the first set of kernel operation parameters; and

performing, by the parameterized run-time configurable kernel, a first kernel operation on the first set of kernel input data to obtain a first set of kernel output data.

17. The non-transitory CRM of claim 16, wherein the instructions further comprise functionality for:

obtaining, from the host application, by the run-time configurable kernel, a second set of kernel operation parameters;

re-parameterizing the run-time configurable kernel, using the second set of kernel operation parameters; and

performing, by the re-parameterized run-time configurable kernel, a second kernel operation on a second set of kernel input data to obtain a second set of kernel output data.

18. The non-transitory CRM of claim 16, wherein the first kernel operation is one selected from the group consisting of a convolutional neural network, a recurrent neural network, a convolution, a de-convolution, a matrix multiplication, and a vector multiplication.

19. The non-transitory CRM of claim 16, wherein the kernel operation parameters comprise at least one selected from the group consisting of a dimensionality of the kernel input data, a dimensionality of the kernel output data, a convolution filter kernel, a convolution filter kernel stride, a pooling stride, a pooling window size, a number of input feature maps, a number of output feature maps, and an output feature map size.

20. The non-transitory CRM of claim 16, wherein the instructions further comprise functionality for, prior to obtaining the first set of kernel input data by the run-time configurable kernel:

programming the kernel into the FPGA by;

deriving, from a kernel template, an FPGA-specific kernel by scaling the kernel template according to the specifications of the FPGA; and

installing the scaled kernel on the FPGA.