MEMORY CONTROLLER UTILIZING AN ERROR CODING DISPERSAL FUNCTION

• US 20160335159A1
• Filed: 08/01/2016
• Published: 11/17/2016
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Grube, Gary W., Markison, Timothy W.
• Granted Patent: US 10,007,574 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A computing core includes memory and a memory controller. The memory is partitioned into a user section and a kernel section. The user section is divided into a first set of pillars and the kernel section is divided into a second set of pillars. The memory controller is operable to dispersed storage error encode a data segment of user data into a set of encoded user data slices. The memory controller is further operable to store the set of encoded user data slices in the first set of pillars of the user section. The memory controller is further operable to dispersed storage error encode a data segment of system data into a set of encoded system data slices. The memory controller is further operable to store the set of encoded system data slices in the second set of pillars of the kernel section.

Claims

1. A computing core comprises:

memory that is partitioned into a user section and a kernel section, wherein the user section is divided into a first set of pillars, wherein the kernel section is divided into a second set of pillars; and

a memory controller operably coupled to the memory, wherein the memory controller is operably to;

dispersed storage error encode a data segment of user data into a set of encoded user data slices;

store the set of encoded user data slices in the first set of pillars of the user section;

dispersed storage error encode a data segment of system data into a set of encoded system data slices; and

store the set of encoded system data slices in the second set of pillars of the kernel section.

2. The computing core of claim 1, wherein the memory comprises one or more of:

a main memory; and

an interface coupling to one or more of a hard disk drive, an external FLASH memory, and an external dispersed storage network (DSN) memory.

3. The computing core of claim 1, wherein the memory controller is further operable to:

retrieve a decode threshold number of encoded user data slices of the set of encoded user data slices from the memory;

dispersed storage error decode the decode threshold number of encoded user data slices to recover the data segment of the user data; and

provide the recovered data segment to a processing module of the computing core.

4. The computing core of claim 1, wherein the memory controller is further operable to:

retrieve a decode threshold number of encoded system data slices of the set of encoded system data slices from the memory;

dispersed storage error decode the decode threshold number of encoded system data slices to recover the data segment of the system data; and

provide the recovered data segment to processing module of the computing core.

5. The computing core of claim 1 further comprises:

the user section is logically divided into the first set of pillars; and

the kernel section is logically divided into the second set of pillars.

6. The computing core of claim 1 further comprises:

the user section is physically divided into the first set of pillars; and

the kernel section is physically divided into the second set of pillars.

7. The computing core of claim 1 further comprises:

the system data including one or more of;

an operating system and an application program interface (API); and

the user data including one or more of;

a user application and a software driver.