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Processing System With Interspersed Processors DMA-FIFO

  • US 20160335207A1
  • Filed: 07/25/2016
  • Published: 11/17/2016
  • Est. Priority Date: 11/21/2012
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a plurality of processors configured to execute at least one program;

    a plurality of memories, wherein each memory of the plurality of memories is coupled to a subset of the plurality of processors;

    a plurality of configurable communication elements, wherein each configurable communication element of the plurality of configurable communication elements includes a plurality of communication ports, a first memory, and a routing engine;

    wherein to execute the at least one program, each processor of the subset of the plurality of processors is configured to communicate with at least one other processor of the subset of the plurality of processors via a particular configurable communication element of the plurality of configurable communication element; and

    a plurality of direct memory access (DMA) engines, wherein each DMA engine of the plurality of DMA engines is configured to transfer data between selected memories of the plurality of memories and selected configurable communication elements of the plurality of configurable communication elements.

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