Processing System With Interspersed Processors DMA-FIFO
First Claim
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1. An apparatus, comprising:
- a plurality of processors configured to execute at least one program;
a plurality of memories, wherein each memory of the plurality of memories is coupled to a subset of the plurality of processors;
a plurality of configurable communication elements, wherein each configurable communication element of the plurality of configurable communication elements includes a plurality of communication ports, a first memory, and a routing engine;
wherein to execute the at least one program, each processor of the subset of the plurality of processors is configured to communicate with at least one other processor of the subset of the plurality of processors via a particular configurable communication element of the plurality of configurable communication element; and
a plurality of direct memory access (DMA) engines, wherein each DMA engine of the plurality of DMA engines is configured to transfer data between selected memories of the plurality of memories and selected configurable communication elements of the plurality of configurable communication elements.
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Abstract
Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.
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Citations
20 Claims
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1. An apparatus, comprising:
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a plurality of processors configured to execute at least one program; a plurality of memories, wherein each memory of the plurality of memories is coupled to a subset of the plurality of processors; a plurality of configurable communication elements, wherein each configurable communication element of the plurality of configurable communication elements includes a plurality of communication ports, a first memory, and a routing engine; wherein to execute the at least one program, each processor of the subset of the plurality of processors is configured to communicate with at least one other processor of the subset of the plurality of processors via a particular configurable communication element of the plurality of configurable communication element; and a plurality of direct memory access (DMA) engines, wherein each DMA engine of the plurality of DMA engines is configured to transfer data between selected memories of the plurality of memories and selected configurable communication elements of the plurality of configurable communication elements. - View Dependent Claims (2, 3, 4)
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5. A method for operating a multiprocessor system, the method comprising:
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executing at least one program on a plurality of processors, each processor comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; wherein executing at least one program comprises; at least a subset of the plurality of processors, each of which coupled to a respective one of a plurality of memories, communicating with each other through a plurality of configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine; and controlling a plurality of direct memory access (DMA) engines coupled to one or more of the plurality of memories, wherein each DMA engine of the plurality of DMA engines is configured to transfer data between selected ones of the communication ports and the plurality of memories. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20)
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18. A system, comprising:
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a plurality of processors configured to execute at least one program; and a plurality of configurable communication elements coupled to the plurality of processors in an interspersed fashion, wherein each configurable communication element includes; a plurality of memories, wherein each memory of the plurality of memories is coupled to a respective processor of the plurality of processors; and a plurality of direct memory access (DMA) engines coupled to one or more of the plurality of memories, wherein each DMA engine of the plurality of DMA engines is configured to transfer data between selected ones of the communication ports and the plurality of memories; wherein to execute the at least one program, each processor of a subset of the plurality of processors is configured to; communicate with at least one other processor of the subset of the plurality of processors via a particular configurable communication element of the plurality of configurable communication element; and control the plurality of direct memory access DMA engines.
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Specification