NEUROMORPHIC COMPUTATIONAL SYSTEM(S) USING RESISTIVE SYNAPTIC DEVICES

• US 20160336064A1
• Filed: 05/16/2016
• Published: 11/17/2016
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Seo, Jae-sun, Yu, Shimeng, Cao, Yu, Vrudhula, Sarma
• Granted Patent: US 9,934,463 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/088 Non-supervised learning, e.g. competitive learning
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods

Abstract

Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

Claims

1. Computational circuitry, comprising:

a cross point resistive network comprising a set of conductive lines and variable resistive units comprises a first set of the variable resistive units coupled to a first conductive line of the set of conductive lines and other sets of the variable resistive units each coupled to a corresponding conductive line of the set of conductive lines, wherein the first set of the variable resistive units is configured to generate a correction line current on the first conductive line and the other sets of the variable resistive units are configured to generate resultant line currents such that each of the other sets of the variable resistive units generates a different one of the resultant line currents on the corresponding conductive line; and

line control circuitry coupled to receive the correction line current and the resultant line currents from the set of conductive lines, wherein the line control circuitry is configured to generate digital vector values such that each of the digital vector values is set in accordance with a difference between a current level of a corresponding resultant line current of the resultant line currents and a current level of the correction line current.

2. The computational circuitry of claim 1 wherein:

the cross point resistive network is arranged such that the variable resistive units are arranged in columns of the variable resistive units;

the first set of the variable resistive units is a first column of the columns of the variable resistive units; and

the other sets of the variable resistive units are other columns of the columns of the variable resistive units such that each other set of the variable resistive units is a corresponding one of the other columns of the variable resistive units.

3. The computational circuitry of claim 2 wherein the line control circuitry comprises subtractors wherein:

the line control circuitry is configured to generate uncorrected digital vector values and a digital correction value such that the digital correction value represents the current level of the correction line current and, for each of the resultant line currents, each of the uncorrected digital vector values represents the current level of the corresponding resultant line current; and

the subtractors are each configured to subtract the digital correction value from a corresponding one of the uncorrected digital vector values so as to generate a corresponding one of the digital vector values.

4. The computational circuitry of claim 3 wherein:

the variable resistive units are configured to provide variable conductances such that each of the variable resistive units is configured to provide a corresponding variable conductance of the variable conductances in any one of a set of conductance states wherein the set of conductance states includes a minimum conductance state and a maximum conductance state; and

the corresponding variable conductance of each of the variable resistive units in the first column of the variable resistive units is provided in the minimum conductance state.

5. The computational circuitry of claim 4 further comprising word line control circuitry wherein:

the cross point resistive network is a cross point resistive array comprising the variable resistive units, the set of conductive lines, a set of word lines, and the set of conductive lines wherein the set of conductive lines is a set of bit lines;

the cross point resistive network is arranged such that the variable resistive units are arranged in rows of the variable resistive units such that each of the rows of the variable resistive units is connected to a corresponding word line in the set of word lines;

the word line control circuitry is connected to the set of word lines, the word line control circuitry being configured to generate word line voltages such that for each of the rows of the variable resistive units, the word line control circuitry is configured to apply a corresponding word line voltage of the word line voltages to the corresponding word line;

the line control circuitry is bit line control circuitry coupled to receive the resultant line currents and the correction line current from the set of bit lines; and

the cross point resistive array is configured to generate the resultant line currents and the correction line current in response to the corresponding word line voltage.

6. The computational circuitry of claim 5 wherein the word line control circuitry is configured to generate the word line voltages such that the word line voltages represent a corresponding vector value of vector values in a vector.

7. The computational circuitry of claim 6 wherein the set of conductance states further includes one or more intermediary conductance states that are greater than the minimum conductance state but less than the maximum conductance state.

8. The computational circuitry of claim 7 further comprising peripheral digital computational circuitry configured to control the word line control circuitry and the bit line control circuitry wherein the peripheral digital computational circuitry is configured such that the word line control circuitry and the bit line control circuitry provide the corresponding variable conductance of each of the variable resistive units in a conductance state of the set of conductance states that represents a corresponding matrix value of matrix values in a matrix.

9. The computational circuitry of claim 8 wherein the peripheral digital computational circuitry is further configured such that the word line control circuitry and the bit line control circuitry generate a set of one or more voltage pulses across one of the variable resistive units in the other columns such that the set of one or more voltage pulses adjust the corresponding variable conductance to an other conductance state of the set of conductance states so that the corresponding matrix value of matrix values in the matrix is updated.

10. The computational circuitry of claim 9 wherein each voltage pulse in the set of one or more voltage pulses has a same temporal duration.

11. The computational circuitry of claim 9 wherein each voltage pulse in the set of one or more voltage pulses is a positive voltage pulse.

12. The computational circuitry of claim 9 wherein each voltage pulse in the set of one or more voltage pulses is a negative voltage pulse.

13. The computational circuitry of claim 10 wherein the set of one or more voltage pulses includes a pulse pair of a positive voltage pulse and a negative voltage pulse.

14. The computational circuitry of claim 13 wherein the positive voltage pulse has a longer pulse duration than the negative voltage pulse and the positive voltage pulse has a voltage magnitude that is greater than a voltage magnitude of the negative voltage pulse.

15. The computational circuitry of claim 13 wherein the negative voltage pulse has a longer pulse duration than the positive voltage pulse and the negative voltage pulse has a voltage magnitude that is greater than a voltage magnitude of the positive voltage pulse.

16. The computational circuitry of claim 9 wherein a pulse duration of each voltage pulse in the set of one or more voltage pulses depends on the conductance state.

17. The computational circuitry of claim 16 wherein the set of one or more voltage pulses is a set of one or more positive voltage pulses.

18. The computational circuitry of claim 16 wherein the set of one or more voltage pulses is a set of one or more negative voltage pulses.

19. The computational circuitry of claim 8 wherein the cross point resistive array comprises variable resistive elements such that the variable resistive units are each provided as one or more of the variable resistive elements.

20. The computational circuitry of claim 8 wherein the cross point resistive array comprises variable resistive elements such that the variable resistive units are each provided as an individual one of the variable resistive elements.

21. The computational circuitry of claim 8 wherein the cross point resistive array comprises variable resistive elements such that the variable resistive units are each provided as a subarray of the variable resistive elements.

22. The computational circuitry of claim 8 wherein the cross point resistive array comprises variable resistive elements and wherein the cross point resistive array is configured such that the variable resistive units are reconfigurable such that each of the variable resistive units are reconfigurable to be different combinations of the variable resistive elements.

23. The computational circuitry of claim 8 wherein the cross point resistive array comprises variable resistive elements such that the variable resistive units are each provided as one or more of the variable resistive elements.