SEMICONDUCTOR DEVICE AND STRUCTURE
First Claim
1. A semiconductor device, comprising:
- a first NMOS transistor;
a second NMOS transistor;
a third NMOS transistor;
a fourth NMOS transistor;
a first PMOS transistor, comprising a gate coupled to a gate of the first NMOS transistor for receiving an input signal;
a second PMOS transistor, comprising a gate coupled to a gate of the second NMOS transistor;
a third PMOS transistor, comprising a gate coupled to a gate of the third NMOS transistor; and
a fourth PMOS transistor, comprising a gate coupled to a gate of the fourth NMOS transistor, and a drain coupled to a drain of the fourth NMOS transistor for providing an output signal;
wherein when the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function,wherein when the first and second NMOS transistors are connected in serial, and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function.
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Accused Products
Abstract
A semiconductor device is provided. Gates of first PMOS and NMOS transistors are coupled together for receiving an input signal. Gates of second PMOS and NMOS transistors are coupled together. Gates of third PMOS and NMOS transistors are coupled together. Gates of fourth PMOS and NMOS transistors are coupled together. Drains of fourth PMOS and NMOS transistors are coupled together for providing an output signal. When the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function. When the first and second NMOS transistors are connected in serial and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function.
9 Citations
20 Claims
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1. A semiconductor device, comprising:
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a first NMOS transistor; a second NMOS transistor; a third NMOS transistor; a fourth NMOS transistor; a first PMOS transistor, comprising a gate coupled to a gate of the first NMOS transistor for receiving an input signal; a second PMOS transistor, comprising a gate coupled to a gate of the second NMOS transistor; a third PMOS transistor, comprising a gate coupled to a gate of the third NMOS transistor; and a fourth PMOS transistor, comprising a gate coupled to a gate of the fourth NMOS transistor, and a drain coupled to a drain of the fourth NMOS transistor for providing an output signal; wherein when the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function, wherein when the first and second NMOS transistors are connected in serial, and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor structure, comprising:
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a semiconductor substrate, comprising; first, second, third, fourth PMOS transistors, wherein the first, second, third and fourth PMOS transistors are disposed in a first row; and first, second, third, fourth NMOS transistors, wherein the first, second, third and fourth NMOS transistors are disposed in a second row adjacent to the first row; a plurality of metal layers on the semiconductor substrate; and an oxide diffusion (OD) layer in the semiconductor substrate, wherein gates of the first PMOS and NMOS transistors are connected together for receiving an input signal through the metal layers, wherein gates of the second PMOS and NMOS transistors are connected together through the metal layers, wherein gates of the third PMOS and NMOS transistors are connected together through the metal layers, wherein gates of the fourth PMOS and NMOS transistors are connected together through the metal layers, and drains of the fourth PMOS and NMOS transistors are connected together for providing an output signal via the metal layer, wherein when the first, second, third and fourth NMOS transistors are connected in parallel through the metal layers and the OD layer, the first, second, third and fourth PMOS transistors are connected in parallel through the metal layers and the OD layer, wherein when the first and second NMOS transistors are connected in serial through the metal layers and the OD layer, the first and second PMOS transistors are connected in serial through the metal layers and the OD layer, wherein when the third and fourth NMOS transistors are connected in serial through the metal layers and the OD layer, the third and fourth PMOS transistors are connected in serial through the metal layers and the OD layer. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification