SEMICONDUCTOR DEVICES WITH SUPERLATTICE LAYERS PROVIDING HALO IMPLANT PEAK CONFINEMENT AND RELATED METHODS

• US 20160336407A1
• Filed: 05/13/2016
• Published: 11/17/2016
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Mears, Robert J., Takeuchi, Hideki
• Granted Patent: US 9,899,479 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/157 Doping structures, e.g. doping superlattices, nipi superlattices delta doping in general H01L29/365
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

a plurality of field effect transistors (FETs) on the semiconductor substrate and each comprising

a gate,

spaced apart source and drain regions on opposite sides of the gate,

upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and

a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.

2. The semiconductor device of claim 1 wherein the upper and lower superlattices each comprises a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

3. The semiconductor device of claim 2 wherein each base semiconductor portion comprises silicon.

4. The semiconductor device of claim 2 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

5. The semiconductor device of claim 2 wherein the at least one non-semiconductor layer comprises oxygen.

6. The semiconductor device of claim 1 wherein the plurality of FETs comprises a plurality of planar CMOS transistors.

7. The semiconductor device of claim 1 wherein each of the FETs has a channel defined in at least a portion of the upper superlattice layer.

8. The semiconductor device of claim 1 wherein each gate comprises a gate oxide layer above the upper superlattice layer, and a gate electrode on the gate oxide layer.

9. A semiconductor device comprising:

a semiconductor substrate; and

a plurality of CMOS transistors on the semiconductor substrate and each comprising

a gate,

spaced apart source and drain regions on opposite sides of the gate,

upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and

a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices;

the upper and lower superlattices each comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

10. The semiconductor device of claim 9 wherein each base semiconductor portion comprises silicon.

11. The semiconductor device of claim 9 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

12. The semiconductor device of claim 9 wherein the at least one non-semiconductor layer comprises oxygen.

13. The semiconductor device of claim 9 wherein the plurality of CMOS transistors comprises a plurality of planar CMOS transistors.

14. The semiconductor device of claim 9 wherein each of the CMOS transisors has a channel defined in at least a portion of the upper superlattice layer.

15. The semiconductor device of claim 9 wherein each gate comprises a gate oxide layer above the upper superlattice layer, and a gate electrode on the gate oxide layer.

16. A method of making semiconductor device comprising:

forming a plurality of field effect transistors (FETs) on a semiconductor substrate, each comprising

a gate,

spaced apart source and drain regions on opposite sides of the gate,

upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and

a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.

17. The method of claim 16 wherein the upper and lower superlattices each comprises a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

18. The method of claim 17 wherein each base semiconductor portion comprises silicon.

19. The method of claim 17 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

20. The method of claim 17 wherein the at least one non-semiconductor layer comprises oxygen.

21. The method of claim 16 wherein forming the plurality of FETs comprises forming a plurality of planar CMOS transistors.