NETWORK COMPUTER SYSTEMS WITH POWER MANAGEMENT

• US 20160342195A1
• Filed: 04/06/2016
• Published: 11/24/2016
• Est. Priority Date: 06/24/2008
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Virident Systems Inc. (Western Digital Corporation)
• Inventors: Karamcheti, Vijay, Okin, Kenneth Alan, Ganapathy, Kumar
• Granted Patent: US 10,156,890 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0674 Disk device
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

Claims

1-56. -56. (canceled)

57. An apparatus comprising:

a network computer system including

a plurality of processor complexes;

a plurality of disk-read-only-memory (disk-ROM) devices shared amongst the plurality of processor complexes;

a power controller coupled to each of the plurality of processor complexes, the power controller to power down one or more processor complexes in response to a reduced computing load; and

wherein the plurality of disk-ROM devices maintain data for one or more processor complexes that remain powered on.

58. The apparatus of claim 57, wherein the power controller executes a centralized network control software driver to make consistent network-level decisions of the one or more processor complexes that remain powered up and the one or more processor complexes that are powered down in response to the computing load on the network computer system.

59. The apparatus of claim 57, wherein the network computer system further includes

a router coupled to the plurality of processor complexes and the plurality of disk-read-only-memory (disk-ROM) devices;

and

an interconnect network coupled between the router, the plurality of processor complexes, and the plurality of disk-read-only-memory (disk-ROM) devices;

wherein the interconnect network to communicate information between the plurality of processor complexes and the plurality of disk-read-only-memory (disk-ROM) devices using one or more packets.

60. The apparatus of claim 59, wherein each processor complex executes a distributed network control software driver that is in communication with the power controller and the other processor complexes to cooperate and make consistent network-level decisions of the one or more processor complexes that remain powered up and the one or more processor complexes that are powered down in response to the computing load on the network computer system.

61. The apparatus of claim 59, wherein each processor complex has a processor address space that includes pointers pointing to a portion of physical address space associated with at least one of the plurality of disk-read-only-memory (disk-ROM) devices.

62. The apparatus of claim 61, wherein each processor complex includes a plurality of processors with each processor having an application memory space pointing to a portion of the processor address space of the processor complex.

63. The apparatus of claim 62, wherein each processor complex includes a plurality of memory devices to provide a physical memory space and wherein each processor complex has processor address space that includes pointers pointing to a portion of physical memory space associated with one or more of the plurality of memory devices.

64. The apparatus of claim 59, wherein

each processor complex includes a cache coherency system;

and

the interconnect network is an external interconnect network not subject to the cache coherency system of each processor complex.

65. The apparatus of claim 64, wherein

each processor complex includes

one or more levels of cache memory/

a cache-coherent interconnect network coupled to the one or more levels of cache memory;

and

a bridge port coupled to and between the external interconnect network and the cache-coherent interconnect network.

66. The apparatus of claim 65, wherein

data in the plurality of disk-read-only-memory (disk-ROM) devices is maintained in a cache coherent state with each processor complex by a mapping software driver executed by each processor complex.