MIGRATING DATA BETWEEN MEMORIES

• US 20160342363A1
• Filed: 01/30/2014
• Published: 11/24/2016
• Est. Priority Date: 01/30/2014
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: KRAUSE, Michael R.
• Granted Patent: US 10,061,532 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0683 Plurality of storage devices

Abstract

A system includes multiple memories. Access of at least one of the multiple memories uses an interface subsystem that includes a memory controller and a distinct media controller, the memory controller to issue a transaction-level access request. The media controller is associated with at least one memory and produces, in response to the transaction-level access request, at least one command according to a specification of the at least one memory. Data is migrated from a first of the multiple memories to a second of the multiple memories, without the data traversing through a cache memory in the processor during the migrating.

Claims

1. A method comprising:

accessing, by a processor in a system, data of at least one of a plurality of memories, the accessing using an interface subsystem that includes a memory controller and a distinct media controller, the memory controller associated with the processor and to issue a transaction-level access request, and the media controller associated with the at least one memory and to produce, in response to the transaction-level access request, at least one command according to a specification of the at least one memory; and

migrating, in the system, data from a first of the plurality of memories to a second of the plurality of memories, without the data traversing through a cache memory in the processor during the migrating.

2. The method of claim 1, wherein migrating the data from the first memory to the second memory comprises migrating the data from the first memory according to a first technology to the second memory according to a second, different technology.

3. The method of claim 1, wherein migrating the data from the first memory to the second memory comprises migrating the data from the first memory at a first memory tier to the second memory at a second, different memory tier.

4. The method of claim 1, wherein the migrating is controlled by machine-readable instructions executable by the processor.

5. The method of claim 1, wherein the migrating is controlled by a memory management entity that is separate from the processor, and the migrating is transparent to the processor.

6. The method of claim 1, further comprising:

initiating migration of the data, wherein the migrating is in response to the initiating; and

in response to the initiating, flushing a portion of content in the cache memory to the first memory, the flushing performed prior to the migrating.

7. The method of claim 1, further comprising:

marking the data as being in active migration; and

in response to receiving a write to the data from an application, trapping the application.

8. The method of claim 1, wherein migrating the data comprises migrating blocks of the data on a block-by-block basis, the method further comprising:

in response to receiving a first request targeting an actively migrated block of the blocks, delaying processing of the first request until migration of the actively migrated block is completed; and

in response to receiving a second request targeting a block, from among the blocks, that is not being actively migrated, processing the second request without delaying the second request.

9. The method of claim 8, wherein delaying the processing of the first request comprises logging the first request for subsequent replay.

10. A system comprising:

a processor including a cache memory;

a plurality of memories;

an interface subsystem including a memory controller associated with the processor and a media controller associated with at least one of the plurality of memories, the memory controller to issue a transaction-level access request that is independent of a specification governing access of the at least one memory, and the media controller to produce, in response to the transaction-level access request, at least one command according to the specification; and

a migration control entity to migrate a page of data from a first of the plurality of memories to a second of the plurality of memories, without the page of data traversing through the cache memory of the processor.

11. The system of claim 10, wherein the migration control entity includes machine-readable instructions executable on the processor.

12. The system of claim 10, wherein the migration control entity is part of a memory management entity that is separate from the processor.

13. The system of claim 10, wherein the page of data is to be migrated from the first memory according to a first technology to the second memory according to a second, different technology.

14. The system of claim 10, wherein the page of data is to be migrated from the first memory at a first memory tier to the second memory at a second, different memory tier.

15. An article comprising at least one machine-readable storage medium storing instructions that upon execution cause a system to:

Initiate data migration in a system including a plurality of memories, wherein access of data in at least one of the plurality of memories uses an interface subsystem that includes a memory controller and a distinct media controller, the memory controller associated with a processor and to issue a transaction-level access request, and the media controller associated with the at least one memory and to produce, in response to the transaction-level access request, at least one command according to a specification of the at least one memory; and

migrate data from a first of the plurality of memories to a second of the plurality of memories, without the data traversing through a cache memory in the processor during the migrating and without the data traversing through any input/output subsystem in the system and any storage subsystem including secondary storage media in the system.