DATA PROTECTION IN A NAMESPACE

• US 20160342463A1
• Filed: 05/20/2015
• Published: 11/24/2016
• Est. Priority Date: 05/20/2015
• Status: Abandoned Application

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OSHIMA, Gen
• Application Number:
  US14/717,658
• Publication Number:
  US 20160342463A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Techniques for managing addresses for a non-volatile semiconductor storage device. The techniques include a method that includes determining an error-correction seed for data for a non-volatile semiconductor storage device based on a first logical address associated with the data that includes a first namespace identifier and a first logical block address. The method also includes converting the first logical address to an internal linear address that does not include the first namespace identifier. The method further includes determining a physical address based on the internal linear address. The method also includes accessing data stored in the non-volatile semiconductor storage device based on the physical address. A storage device and non-transitory computer readable medium are also provided.

Claims

1. A data storage device comprising:

a non-volatile semiconductor storage device; and

a controller configured to;

determine an error-correction seed for data for the non-volatile semiconductor storage device based on a first logical address associated with the data that includes a first namespace identifier and a first logical block address,

convert the first logical address to an internal linear address that does not include the first namespace identifier,

determine a physical address based on the internal linear address, and

access data stored in the non-volatile semiconductor storage device based on the physical address.

2. The data storage device of claim 1, wherein:

the error-correction seed comprises a cyclic redundancy check seed; and

the controller is further configured to perform cyclic redundancy check operations on data stored in the flash memory device.

3. The data storage device of claim 1, wherein:

the controller is configured to convert the first logical address to the internal linear address by converting the first namespace identifier to an internal linear base address based on a namespace identifier lookup table and to add the first logical block address to the internal linear base address to obtain the internal linear address.

4. The data storage device of claim 1, wherein the controller is further configured to:

perform one or more flash translation layer operations with the first logical address.

5. The data storage device of claim 4, wherein the one or more flash translation layer operations comprises a log block operation.

6. The data storage device of claim 1, wherein the controller is configured to determine the physical address based on a logical address to physical address conversion table.

7. The data storage device of claim 1, wherein:

the first logical block address indicates a location of a block in a logical address space; and

the internal logical address indicates a location of a sector in an internal logical address space.

8. The data storage device of claim 1, wherein:

the first namespace identifier is associated with a first namespace that spans a first range within an internal logical address space associated with the internal logical address, and

a second range within the internal logical address space is associated with a second namespace.

9. The data storage device of claim 8, wherein the controller is further configured to:

resize the first namespace by adjusting an end address in the internal logical address space associated with the first namespace and by adjusting a beginning address in the internal logical address space associated with the second namespace.

10. A method, comprising:

determining an error-correction seed for data for a non-volatile semiconductor storage device based on a first logical address associated with the data that includes a first namespace identifier and a first logical block address,

converting the first logical address to an internal linear address that does not include the first namespace identifier,

determining a physical address based on the internal linear address, and

accessing data stored in the non-volatile semiconductor storage device based on the physical address.

11. The method of claim 10, wherein:

the error-correction seed comprises a cyclic redundancy check seed; and

the method further comprises performing cyclic redundancy check operations on data stored in the flash memory device.

12. The method storage device of claim 10, wherein converting the first logical address to the internal linear address comprises:

converting the first namespace identifier to an internal linear base address based on a namespace identifier lookup table; and

adding the first logical block address to the internal linear base address to obtain the internal linear address.

13. The method of claim 10, further comprising:

performing one or more flash translation layer operations with the first logical address.

14. The method of claim 13, wherein the one or more flash translation layer operations comprises a log block operation.

15. The method of claim 10, further comprising:

determining the physical address based on a logical address to physical address conversion table.

16. The method of claim 10, wherein:

the first logical block address indicates a location of a block in a logical address space; and

the internal linear address indicates a location of a sector in an internal linear address space.

17. The method of claim 10, wherein:

the first namespace identifier is associated with a first namespace that spans a first range within an internal linear address space associated with the internal linear address, and

a second range within the internal linear address space is associated with a second namespace.

18. The method of claim 17, further comprising:

resizing the first namespace by adjusting an end address in the internal linear address space associated with the first namespace and by adjusting a beginning address in the internal logical address space associated with the second namespace.

19. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method comprising:

determining an error-correction seed for data for a non-volatile semiconductor storage device based on a first logical address associated with the data that includes a first namespace identifier and a first logical block address,

converting the first logical address to an internal linear address that does not include the first namespace identifier,

determining a physical address based on the internal linear address, and

accessing data stored in the non-volatile semiconductor storage device based on the physical address.

20. The non-transitory computer-readable medium of claim 19, wherein:

the error-correction seed comprises a cyclic redundancy check seed; and

the method further comprises performing cyclic redundancy check operations on data stored in the flash memory device.