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SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

  • US 20160343414A1
  • Filed: 10/20/2015
  • Published: 11/24/2016
  • Est. Priority Date: 05/20/2015
  • Status: Active Grant
First Claim
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1. A semiconductor memory device, comprising:

  • a memory cell array including a plurality of pages;

    a peripheral circuit suitable for performing a program operation and a read operation on the memory cell array; and

    a control logic suitable for controlling the peripheral circuit to apply first and second pass voltages respectively to first and second word lines adjacent to a selected word line during a program verify operation or the read operation.

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