COMPLEMENTARY BIPOLAR SRAM

• US 20160343427A1
• Filed: 07/07/2015
• Published: 11/24/2016
• Est. Priority Date: 05/20/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ning, Tak H.
• Granted Patent: US 9,653,149 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/411 using bipolar transistors only
• CPC Class Codes: G11C 11/4116 with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL
• CPC Class Codes: G11C 11/416 Read-write [R-W] circuits
• CPC Class Codes: H01L 21/8228 Complementary devices, e.g. complementary transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/10 SRAM devices comprising bipolar components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A complementary lateral bipolar SRAM device and method of operating. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.

Claims

1. A method of manufacturing a memory cell comprising:

forming a first set of lateral bipolar transistors on a semiconductor substrate, the first set of lateral bipolar transistors forming a first inverter device, and

forming a second set of lateral bipolar transistors on the substrate, the second set of lateral bipolar transistors forming a second inverter device, wherein a first bipolar transistor of each said first set and second set is an PNP type bipolar transistor having a base terminal, an emitter terminal and a collector terminal, and a second bipolar transistor of each said first set and second set being a NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal, the first inverter device and second inverter device configured in a cross-coupled configuration to store a logic state;

forming a first conductor layer that electrically couples the emitter terminal of said PNP type transistor of said first inverter device to said emitter terminal of said PNP type transistor of said second inverter device;

forming a second conductor layer that electrically couples the first emitter terminal of said NPN transistor of said first inverter device to the first emitter terminal of said NPN transistor of said second inverter device; and

forming a third conductor layer that electrically couples said second emitter terminal of said NPN bipolar transistor of said first inverter to a bit line true (BLT) conductor; and

forming a fourth conductor layer that electrically couples said second emitter terminal of said lateral NPN bipolar transistor of said second inverter device to a bit line complement (BLC) conductor.

2. The method of claim 1, wherein said forming said first inverter device comprises:

forming a fifth conductor layer that electrically couples the base terminal of said PNP type bipolar transistor to the base terminal of said NPN type bipolar transistor in the first inverter device, and forming a sixth conductor layer that electrically couples the collector terminal of said PNP type bipolar transistor to the collector terminal of said NPN type bipolar transistor in the first inverter device, and

said forming said second inverter device comprises;

forming a seventh conductor layer that electrically couples the base terminal of said PNP type bipolar transistor to the base terminal of said NPN type bipolar transistor in the second inverter device and forming an eighth conductor layer that electrically couples the collector terminal of said PNP type bipolar transistor to the collector terminal of said NPN type bipolar transistor in the second inverter device.

3. The method of claim 2, wherein to configure said first inverter device and second inverter device in said cross-coupled configuration comprises:

forming a ninth conductor layer that electrically couples the fifth conductor coupling said base terminals of said first inverter device to said eighth conductor layer that electrically couples said collector terminals of said second inverter device;

forming a tenth conductor layer that electrically couples the seventh conductor coupling said base terminals of said second inverter device to said sixth conductor layer that electrically couples the collector terminals of said first inverter device.

4. A method of operating a memory cell, the memory cell comprising:

a first set of lateral bipolar transistors fabricated on a semiconductor substrate, the first set of lateral bipolar transistors forming a first inverter device, and a second set of lateral bipolar transistors fabricated on the semiconductor substrate, the second set of lateral bipolar transistors forming a second inverter device, the first inverter device and second inverter device in a cross-coupled configuration to store a logic state;

a first bipolar transistor of each said first set and second set being an PNP type bipolar transistor having a base terminal, an emitter terminal and a collector terminal, and a second bipolar transistor of each said first set and second set being a NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal,

a first conductor electrically coupling an emitter terminal of said PNP type transistor of said first inverter device and said emitter terminal of said PNP type transistor of said second inverter device, said first conductor adapted to receive a first applied voltage; and

a second conductor electrically coupling the first emitter terminal of said NPN transistor of said first inverter device and the first emitter terminal of said NPN transistor of said second inverter device, said second conductor adapted to receive a second applied voltage,

wherein said second emitter terminal of said NPN bipolar transistor of said first inverter device is electrically coupled to a bit line true conductor (BLT) for controlling electrical impedance from the first inverter to said BLT conductor, and said second emitter terminal of said NPN bipolar transistor of said second inverter device is electrically coupled to a bit line complement conductor (BLC) for controlling electrical impedance from the second inverter device to said BLC conductor, each said BLT and BLC conductors used to access said stored logic state, wherein said method comprises;

applying a first voltage to said first conductor;

applying a second voltage to said second conductor, wherein one NPN type transistor of either said first inverter device or second inverter device becomes activated responsive to application of said first voltage and second voltage such that electrical current flows through said first emitter terminal of said activated NPN transistor device to said second conductor, and

applying a further voltage to each said respective said BLT conductor and BLC conductor to write a logic state value to or read a logic state value from said memory cell.

5. The method of operating a memory cell of claim 4, comprising:

placing said memory cell in a standby state with one NPN bipolar transistor of either said first inverter device or second inverter device in said activated state, said placing comprising;

applying a first voltage to said first conductor, and

applying said second voltage to said second conductor such that said applied first voltage is of a value greater than a value of said second voltage;

applying a voltage at each respective said BLT conductor and BLC conductor at a value such that no current flows from said second emitter terminal of said NPN bipolar transistor of said first inverter device to said bit line true (BLT) conductor, and no current flows from said second emitter terminal of said NPN bipolar transistor of said second inverter device to said bit line complement (BLC) conductor.

6. The method of operating a memory cell of claim 5, wherein said applied first voltage is greater than said applied second voltage by a value of at least a multiple of a quantity kT/q volts where k is a Boltzmann constant, T is a temperature value, and q is an electrical charge.

7. The method of operating a memory cell of claim 6, wherein a plurality of memory cells are connected to said wordline conductor, said method further comprising:

selecting said plurality of memory cells on the wordline, said selecting comprising;

maintaining a voltage applied at each respective said BLT conductor and BLC conductor at their standby state voltage level values;

raising said first voltage applied to said first conductor to a raised first voltage value, and

raising said second voltage applied to said second conductor to a raised second voltage value, said raised first voltage and raised second voltage values being such that no current flows through said second emitter terminal of said NPN bipolar transistor of said first inverter device to said bit line true (BLT) conductor, and no current flows from said second emitter terminal of said NPN bipolar transistor of said second inverter device to said bit line complement (BLC) conductor, and

one NPN bipolar transistor of either said first inverter device or second inverter device being in an activated state and providing a current flow from said first emitter terminal to said second conductor while the other NPN bipolar transistor of either said second inverter device or first inverter device is non-activated.

8. The method of operating a memory cell of claim 7, further comprising:

reading a logic state value stored within a selected cell, said reading comprising;

reducing the voltage values applied at each respective said BLT conductor and BLC conductor to below their standby state voltage level values, said reduced voltage applied at each respective said BLT conductor and BLC conductor being such that each said NPN bipolar transistor of one of said first inverter device or second inverter device remains activated, wherein, for said activated NPN bipolar transistor, a current flows from said second emitter terminal of said activated NPN bipolar transistor to its coupled said BLT conductor or BLC conductor; and

for a non-activated NPN bipolar transistor, a negligible current flows from said second emitter terminal to its coupled said BLC conductor or BLT conductor.

9. The method of operating a memory cell of claim 8, wherein a voltage at a base terminal of said activated NPN bipolar transistor is substantially equal to said raised first voltage value, and a voltage at a base terminal of said non-activated NPN bipolar transistor is substantially equal to said raised second voltage value, wherein

a voltage applied across said base terminal and second emitter terminal of said activated NPN bipolar transistor is approximately equal to a voltage difference between the raised first voltage value and the lowered voltage value of its coupled one of:

BLT or BLC conductor, and

a voltage applied across said base terminal and second emitter terminal of said non-activated NPN bipolar transistor is approximately equal to a voltage difference between the raised second voltage value and the lowered voltage value applied at its coupled one of;

BLC or BLT conductor.

10. The method of operating a memory cell of claim 7, further comprising:

writing a logic state value for storage within a selected cell, said writing comprising;

deactivating the one NPN bipolar transistor of either said first inverter device or second inverter device that is in said activated state, and

activating the other NPN bipolar transistor of either said second inverter device or first inverter device that is in said non-activated state.

11. The method of operating a memory cell of claim 10, wherein said deactivating the one activated NPN bipolar transistor comprises:

maintaining said one of said BLT or BLC voltage value applied at the respective BLT conductor or BLC conductor coupled to said second emitter terminal of said activated NPN bipolar transistor when in said standby state;

reducing the other one of BLC or BLT voltage value applied at the respective BLC or BLT conductor coupled to said second emitter terminal of said non-activated NPN bipolar transistor to a voltage value equal to said second voltage value applied to said second conductor when in said standby state, thereby activating said non-activated NPN bipolar transistor and deactivating the one activated NPN bipolar transistor.

12. The method of operating a memory cell of claim 11, further comprising:

returning said other one of BLC or BLT voltage value applied at the respective BLC or BLT conductor coupled to said second emitter terminal of said activated NPN bipolar transistor to its standby voltage value; and

applying the first voltage to said first conductor at its standby state value, and

applying said second voltage to said second conductor at said standby state value such that said applied first voltage is of a value greater than a value of said second voltage.