IMPLANT-FREE PUNCH THROUGH DOPING LAYER FORMATION FOR BULK FINFET STRUCTURES

• US 20160343623A1
• Filed: 05/21/2015
• Published: 11/24/2016
• Est. Priority Date: 05/21/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Fogel, Keith E., Reznicek, Alexander, Sadana, Devendra K., Schepis, Dominic J.
• Granted Patent: US 9,514,995 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Claims

1-12. -12. (canceled)

13. A semiconductor structure comprising:

a semiconductor substrate having a top surface and first and second regions;

a plurality of parallel semiconductor fins extending from the top surface of the semiconductor substrate, one or more of the plurality of parallel semiconductor fins extending from the first region and one or more of the plurality of parallel semiconductor fins extending from the second region, the plurality of parallel semiconductor fins defining a plurality of channels;

a p-type punch through stop layer within the first region of the semiconductor substrate and the one or more parallel semiconductor fins extending from the first region, the p-type punch through stop layer including diffused p-type dopants;

an n-type punch through stop layer within the second region of the semiconductor substrate and the one or more parallel semiconductor fins extending from the second region, the n-type punch through stop layer including diffused n-type dopants;

an undoped oxide layer partially filling the plurality of channels;

a p-doped oxide layer partially filling the channels above the first region, the p-doped oxide layer directly contacting the top surface of the semiconductor substrate and the semiconductor fins extending from the first region; and

an n-doped oxide layer partially filling the channels above the second region, the n-doped oxide layer directly contacting the top surface of the semiconductor substrate and the semiconductor fins extending from the second region.

14. The semiconductor structure of claim 13, wherein semiconductor substrate comprises a bulk silicon substrate.

16. The semiconductor structure of claim 13, wherein the p-doped oxide layer consists essentially of borosilicate glass and the n-doped oxide layer consists essentially of phosphosilicate glass or arsenosilicate glass.

17. The structure of claim 16, wherein the one or more parallel semiconductor fins extending from the first region are strained silicon fins and the one or more parallel semiconductor fins extending from the second region are strained silicon germanium fins.

18. The structure of claim 17 wherein the semiconductor substrate comprises a silicon germanium strain relaxed buffer layer.

19. The structure of claim 17, wherein the p-doped oxide layer is thicker than the n-doped oxide layer.

20. The structure of claim 17, wherein the p-type punch through stop layer and then-type punch through stop layer extend substantially equal distances into the plurality of parallel semiconductor fins.

15. (canceled)