SEMICONDUCTOR DEVICE AND STRUCTURE
First Claim
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1. A semiconductor device, comprising:
- a first memory cell comprising a first transistor;
a second memory cell comprising a second transistor,wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor; and
a plurality of junctionless transistors,wherein at least one of said junctionless transistors controls access to at least one of said memory cells.
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Abstract
A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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a first memory cell comprising a first transistor; a second memory cell comprising a second transistor, wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor; and a plurality of junctionless transistors, wherein at least one of said junctionless transistors controls access to at least one of said memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device, comprising:
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an electrically controlled resistive structure; a first memory cell comprising a first transistor; and a second memory cell comprising a second transistor, wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor, and wherein said electrically controlled resistive structure could be set to conduct a signal to said first transistor. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor device, comprising:
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a first memory cell comprising a first transistor; and a second memory cell comprising a second transistor, wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor, and wherein said first transistor comprises a silicided source and drain. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification