Still Block Detection in a Video Sequence

• US 20160345021A1
• Filed: 05/20/2015
• Published: 11/24/2016
• Est. Priority Date: 05/20/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Morgan, Daniel Jay, Kempf, Jeffrey Matthew
• Granted Patent: US 9,832,484 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04N 19/53 Multi-resolution motion estimation; Hierarchical motion estimation

Abstract

A video display system is configured to receive a sequence of image frames. Each frame is divided into a set of blocks. A center of mass is calculated for each block in a first frame and is saved for all blocks in the first frame. A center of mass is calculated for each block in a second frame. Motion between the first frame and the second frame is detected by comparing the center of mass of each block in the second frame to the center of mass of the corresponding block in the first frame, in which a still block is detected when a corresponding block in the first frame and the second frame have a same center of mass, and in which motion in a block is detected when a corresponding block in the first frame and the second frame have a different center of mass.

Claims

1. A method for operating a video display system, the method comprising:

receiving a sequence of image frames;

dividing each frame into a set of blocks as it is received;

calculating a center of mass for each block in a first frame and saving the center of mass for all blocks in the first frame;

calculating a center of mass for each block in a second frame; and

detecting motion between the first frame and the second frame by comparing the center of mass of each block in the second frame to the center of mass of the corresponding block in the first frame, in which a still block is detected when a corresponding block in the first frame and the second frame have a same center of mass, and in which motion in a block is detected when a corresponding block in the first frame and the second frame have a different center of mass.

2. The method of claim 1, further including reducing power to a circuit module in the video display system in response to detecting at least one still block in the second frame.

3. The method of claim 2, in which power to the circuit module is reduced during a time scheduled for processing still blocks in the second frame and not reduced during a time scheduled for processing blocks with motion in the second frame.

4. The method of claim 2, in which power to the circuit module is reduced during a time scheduled for processing the entire second frame when all of the blocks in the second frame are still.

5. The method of claim 1, in which the center of mass of a first block is determined by:

summing a value of all pixels in each row of pixels in the first block to form a separate summation value for each row; and

selecting the row having the largest summation value as the vertical center of mass value for the first block.

6. The method of claim 1, in which the center of mass of a first block is determined by:

multiplying a value of each pixel in the first block by its horizontal location to form a weighted pixel summation value; and

summing all of the weighted pixel values in the first block.

7. The method of claim 6, further including:

summing a value of each pixel in the first block to form a non-weighted pixel summation value; and

normalizing the weighted pixel summation value by the non-weighted pixel summation value to form a horizontal center of mass value for the first block.

8. The method of claim 1, further including converting a video format of the sequence of image frames into a luminance/chroma format, in which the center of mass for each block is based on the luminance values of the pixels in each block.

9. The method of claim 1, further including:

detecting a cadence of repeated image frames by determining a repeating pattern of image frames in which all blocks within the frame are still blocks; and

reducing power to a circuit module in the video display system in accordance to the cadence pattern, such that power is reduced during a time scheduled for processing each repeated image frame.

10. The method of claim 1, further including designating a set of still blocks surrounding each non-still block as motion blocks to compensate for latency between the first frame and the second frame.

11. A method for operating a video display system, the method comprising:

receiving a sequence of image frames;

dividing a each frame into a set of blocks as it is received;

calculating a center of mass for each block in the sequence of image frames, in which a y coordinate of the center of mass of a first block is determined by summing a value of all pixels in each row of pixels in the first block to form a separate summation value for each row; and

selecting the row having the largest summation value as the vertical center of mass value for the first block; and

in which

an x coordinate of the center of mass of the first block is determined by multiplying a value of each pixel in the first block by its horizontal location to form a weighted pixel summation value, and summing all of the weighted pixel values in the first block; and

detecting motion between a first frame and a second frame by comparing the center of mass of each block in the second frame to the center of mass of the corresponding block in the first frame, in which a still block is detected when a corresponding block in the first frame and the second frame have a same center of mass, and in which motion in a block is detected when a corresponding block in the first frame and the second frame have a different center of mass.

12. The method of claim 11, further including:

summing a value of each pixel in the first block to form a non-weighted pixel summation value; and

normalizing the weighted pixel summation value by the non-weighted pixel summation value to form the x coordinate of the center of mass for the first block.

13. The method of claim 11, further including reducing power to a circuit module in the video display system in response to detecting at least one still block in the second frame.

14. The method of claim 13, in which power to the circuit module is reduced during a time scheduled for processing the entire second frame when all of the blocks in the second frame are still.

15. The method of claim 11, further including converting a video format of the sequence of image frames into a luminance/chroma format, in which the center of mass for each block is based on the luminance values of the pixels in each block.

16. A device for processing image data comprising:

a data port configured to receive a sequence of image frames;

image processing logic configured to process each received image frame to form a processed image frame;

a frame buffer configured to receive the processed image frame;

segregation logic configured to divide each received image frame into a set of blocks;

center of mass (COM) logic configured to calculate a COM value for each block;

storage logic configured to store the COM values for all of the blocks in a first frame;

still block detection logic configured to detect motion between the first frame and a second frame by comparing the center of mass of each block in the second frame to the center of mass of the corresponding block in the first frame, in which a still block is detected when a corresponding block in the first frame and the second frame have a same center of mass, and in which motion in a block is detected when a corresponding block in the first frame and the second frame have a different center of mass; and

control logic configured to reduce power to the image processing logic in response to detection of a still block.

17. The device of claim 16, in which power to the image processing logic is reduced during a time scheduled for processing still blocks in the second frame and not reduced during a time scheduled for processing blocks with motion in the second frame.

18. The device of claim 16, in which the COM logic is configured to:

calculate a y coordinate of a COM of a first block by summing a value of all pixels in each row of pixels in the first block to form a separate summation value for each row, and selecting the row having the largest summation value as the vertical center of mass value for the first block; and

calculate an x coordinate of a COM value of the first block by multiplying a value of each pixel in the first block by its horizontal location to form a weighted pixel summation value, and summing all of the weighted pixel values in the first block.

19. The device of claim 16, further including a projector device coupled to receive the processed image data from the frame buffer.

20. The device of claim 16, further including a screen display coupled to receive the processed image data from the frame buffer.