WARP CLUSTERING

• US 20160349832A1
• Filed: 05/26/2015
• Published: 12/01/2016
• Est. Priority Date: 05/26/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JIAO, Yang
• Granted Patent: US 9,804,666 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Units of shader work, such as warps or wavefronts, are grouped into clusters. An individual vector register file of a processor is operated as segments, where a segment may be independently operated in an active mode or a reduced power data retention mode. The scheduling of the clusters is selected so that a cluster is allocated a segment of the vector register file. Additional sequencing may be performed for a cluster to reach a synchronization point. Individual segments are placed into the reduced power data retention mode during a latency period when the cluster is waiting for execution of a request, such as a sample request.

Claims

1. A method of reducing power consumption in a shader of a graphics processing system, comprising:

allocating a segment of a vector register file as a resource for a cluster of shader units of work assigned to a processor and having temporal locality and spatial locality; and

in response to the cluster being in an inactive state, placing the segment of the vector register file associated with the cluster in a reduced power data retention mode.

2. The method of claim 1, wherein the cluster is placed into the inactive state in response to completion of sending texture sample or memory load store commands of the cluster to an external unit.

3. The method of claim 1, wherein the cluster is placed into the inactive state in response to completion of sending texture sample or memory load store commands of the cluster to a texture unit and during at least a portion of a latency period for a texture load.

4. The method of claim 1, wherein the vector register file is used as a resource for units of shader work in which each unit of shader work comprises a group of shader threads to perform Single Instruction Multiple Thread (SIMT) processing.

5. The method of claim 1, wherein the vector register file is organized into a plurality of segments of physical memory, with each segment having an activated mode and a reduced power data retention mode independently selectable from other segments of the vector register file, the method further comprising:

allocating each segment to a respective one of a plurality of different clusters of multiple shader units of work assigned to a particular processor and having temporal locality and spatial locality;

scheduling execution of the different clusters in a sequence; and

placing the segment of each inactive cluster into the reduced power data retention mode during at least a portion of a latency period for a texture load for the respective cluster.

6. The method of claim 1, further comprising prioritizing the shader units of work within the cluster to reach a synchronization point for loading a texture sample.

7. The method of claim 1, wherein the cluster of shader units of work are assigned to consecutive shader tasks of a shader stage.

8. The method of claim 1, wherein each shader unit of work is a unit of thread scheduling.

11. The method of claim 1, with the data segment of each cluster awaiting a data load placed into the lower power data retention mode.

9. A method of reducing power consumption in a shader of a graphics processing system, comprising:

scheduling clusters of shader work for a plurality of processors, each cluster including a plurality of shader units of work assigned to a processor and having temporal locality and spatial locality;

for each cluster, allocating a respective segment of physical memory of a vector register file as a resource, each segment having an active mode and a reduced power data retention mode independently selectable from other segments; and

rotating execution of the clusters and placing segments of inactive clusters into the reduced power data retention mode.

10. The method of claim 9, wherein segments of inactive clusters are placed into the reduced power data retention mode during at least a latency for a data access.

12. The method of claim 9, wherein the vector register file is used as a resource for units of shader work in which each unit of shader work has a group of shader threads to perform Single Instruction Multiple Thread (SIMT) processing.

13. The method of claim 9, further comprising prioritizing the shader units of work within each cluster to reach a synchronization point for loading a texture sample.

14. The method of claim 9, wherein the cluster of multiple shader units of work are assigned to consecutive shader tasks of a shader stage.

15. The method of claim 9, wherein each shader unit of work is a unit of thread scheduling.

16. A graphics processing unit, comprising;

a plurality of programmable processors to perform Single Instruction Multiple Thread (SIMT) processing of shading instructions;

each programmable processor including a vector register file having a plurality of data segments, each segment having an active mode and a reduced power data retention mode independently selectable from other segments;

a scheduler to schedule clusters of shader work for the plurality of programmable processors, each cluster including a plurality of shader units of work assigned to an individual processor and having temporal locality and spatial locality, with each cluster supported by a segment of the vector register file of the assigned individual processor; and

the scheduler selecting a schedule to rotate execution of the clusters to place segments of inactive clusters into the reduced power data retention mode.

17. The graphics processing unit of claim 16, further comprising a sequencer to prioritize the shader units of work within each cluster to reach a synchronization point.

18. The graphics processing unit of claim 16, further comprising a load and store unit to access an external memory, wherein segments of inactive clusters are placed into the reduced power data retention mode during at least a portion of a latency period associated with accessing the external memory for a cluster.

19. The graphics processing unit of claim 16, wherein the external memory comprises a texture unit and segments of inactive clusters are placed in the reduced power data retention mode during at least a portion of a latency period associated with accessing the external memory for a texture access of a cluster.

20. A graphics processing unit, comprising:

a shader including a programmable processing element;

a vector register file used as a resource for units of shader work in which each unit of shader work has a group of shader threads to perform Single Instruction Multiple Thread (SIMT) processing and multiple groups of shader threads are formed into a cluster, the vector register file allocated as a plurality of individual segments; and

a scheduler to group clusters of units of shader work and select a schedule to assign an individual cluster to a segment of the register file and place the segment into a reduced power data retention mode during a latency period when the cluster is waiting for a result of a sample request.