MEMORY SYSTEM

• US 20160350003A1
• Filed: 02/08/2016
• Published: 12/01/2016
• Est. Priority Date: 05/29/2015
• Status: Abandoned Application

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KANNO, Shinichi
• Application Number:
  US15/018,097
• Publication Number:
  US 20160350003A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller executes data transfer between a host and the memory in response to a command from the host. The controller manages first translation information indicating a relation between logical location information and physical location information. In a case where the controller stores first data to the memory, the controller updates second translation information. The first data is included in a data group received from the host in a first write mode, and the second translation information is a copy of the first translation information. In a case where the first write mode is terminated, the controller reflects the second translation information in the first translation information.

Claims

1. A memory system connectable to a host, comprising:

a nonvolatile memory; and

a controller executes data transfer between the host and the memory in response to a command from the host and manages first translation information indicating a relation between logical location information and physical location information, the logical location information being location information designated from the host, the physical location information being location information indicating a physical location in the memory,

wherein in a case where the controller stores first data to the memory, the controller updates second translation information, and the first data is included in a data group received from the host in a first write mode, and the second translation information is a copy of the first translation information, and

in a case where the first write mode is terminated, controller reflects the second translation information in the first translation information.

2. The memory system according to claim 1, wherein in a case where the controller executes data transfer from the memory to the host, the controller obtains physical location information with respect to a data transfer destination in the memory by referring to the first translation information.

3. The memory system according to claim 2, wherein in a case where the controller stores second data to the memory, the controller updates the first translation information, and the second data is data received from the host in a second write mode different from the first write mode.

4. The memory system according to claim 1, wherein the controller receives an end command, and reflects the second translation information in the first translation information in response to reception of the end command.

5. The memory system according to claim 4, wherein the controller reflects the second translation information in the first translation information after the end command is received and after the second translation information is updated with respect to last first data of the data group.

6. The memory system according to claim 1, wherein the controller receives a plurality of the data groups in parallel, and generates the second translation information for each data group.

7. The memory system according to claim 6, wherein the controller receives an end command for each data group, and reflects second translation information of a data group corresponding to the received end command in the first translation information.

8. The memory system according to claim 7, wherein the controller updates the second translation information of the data group corresponding to the received end command in accordance with last first data of the data group corresponding to the received end command, and thereafter, reflects the second translation information related to a data group corresponding to the received end command in the first translation information.

9. The memory system according to claim 8, wherein the end command includes identification information for identifying a corresponding data group.

10. The memory system according to claim 1, wherein a total size of the first data which the controller is capable of receiving from a start of the data group to an end of the data group is equal to or less than an over-provisioning capacity of the memory system.