BUFFERING DATA TO BE WRITTEN TO AN ARRAY OF NON-VOLATILE STORAGE DEVICES

• US 20160350009A1
• Filed: 05/29/2015
• Published: 12/01/2016
• Est. Priority Date: 05/29/2015
• Status: Abandoned Application

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: CERRETA, WILLIAM P., KIRKPATRICK, PETER E., COLGROVE, JOHN
• Application Number:
  US14/725,278
• Publication Number:
  US 20160350009A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

Buffering data to be written to an array of non-volatile storage devices, including: receiving a request to write data to the array of non-volatile storage devices; sending, to a non-volatile random access memory (‘NVRAM’) device, an instruction to write the data to dynamic random access memory (‘DRAM’) in the NVRAM device, the DRAM configured to receive power from a primary power source, the DRAM further configured to receive power from a backup power source in response to the primary power source failing; and writing the data to the DRAM in the NVRAM device.

Claims

1. A method of buffering data to be written to an array of non-volatile storage devices in a multi-array system, the method comprising:

receiving, by a storage array controller in a first storage array, a request to write data to non-volatile storage devices in the first storage array;

sending, from the storage array controller in the first storage array to a non-volatile random access memory (‘

NVRAM’

) storage device in the first storage array, an instruction to write the data to dynamic random access memory (‘

DRAM’

) in the NVRAM storage device in the first storage array, wherein;

the DRAM is configured to receive power from a primary power source, and the DRAM is further configured to receive power from a backup power source in response to the primary power source failing;

the NVRAM storage device in the first storage array is available for exclusive use by one or more storage array controllers in the first storage array; and

the multi-array system includes a second storage array that includes a plurality of non-volatile storage devices and an NVRAM storage device in the second storage array, the NVRAM storage device in the second storage array available for exclusive use by one or more storage array controllers in the second storage array;

writing the data to the DRAM in the NVRAM storage device in the first storage array.

2. The method of claim 1 further comprising:

determining whether the primary power source has failed; and

responsive to determining that the primary power source has failed, writing data contained in the DRAM in the NVRAM storage device in the first storage array to flash memory in the NVRAM storage device in the first storage array.

3. The method of claim 1 wherein each NVRAM storage device includes a plurality of data communications ports, wherein:

the NVRAM storage device in the first storage array is coupled to a first storage array controller in the first storage array via a first data communications port and the NVRAM storage device in the first storage array is coupled to a second storage array controller in the first storage array via a second data communications port; and

the NVRAM storage device in the second storage array is coupled to a first storage array controller in the second storage array via a first data communications port and the NVRAM storage device in the second storage array is coupled to a second storage array controller in the second storage array via a second data communications port.

4. The method of claim 1 wherein the DRAM in the NVRAM storage device in the first storage array includes one or more non-volatile dual in-line memory modules (‘

NVDIMMs’

).

5. The method of claim 1 wherein the backup power source includes a supercapacitor.

6. The method of claim 1 further comprising responsive to writing the data to the DRAM in the NVRAM storage device in the first storage array, sending an acknowledgment indicating that the data has been written to the first storage array.

7. A system for buffering data to be written to an array of non-volatile storage devices in a multi-array system, the system configured to carry out the steps of:

receiving, by a storage array controller in a first storage array, a request to write data to non-volatile storage devices in the first storage array;

sending, from the storage array controller in the first storage array to a non-volatile random access memory (‘

NVRAM’

) storage device in the first storage array, an instruction to write the data to dynamic random access memory (‘

DRAM’

) in the NVRAM storage device in the first storage array, wherein;

the DRAM is configured to receive power from a primary power source, and the DRAM is further configured to receive power from a backup power source in response to the primary power source failing;

the NVRAM storage device in the first storage array is available for exclusive use by one or more storage array controllers in the first storage array; and

the multi-array system includes a second storage array that includes a plurality of non-volatile storage devices and an NVRAM storage device in the second storage array, the NVRAM storage device in the second storage array available for exclusive use by one or more storage array controllers in the second storage array;

writing the data to the DRAM in the NVRAM storage device in the first storage array.

8. The system of claim 7 further configured to carry out the steps of:

determining whether the primary power source has failed; and

responsive to determining that the primary power source has failed, writing data contained in the DRAM in the NVRAM storage device in the first storage array to flash memory in the NVRAM storage device in the first storage array.

9. The system of claim 7 wherein each NVRAM storage device includes a plurality of data communications ports, wherein:

the NVRAM storage device in the first storage array is coupled to a first storage array controller in the first storage array via a first data communications port and the NVRAM storage device in the first storage array is coupled to a second storage array controller in the first storage array via a second data communications port; and

the NVRAM storage device in the second storage array is coupled to a first storage array controller in the second storage array via a first data communications port and the NVRAM storage device in the second storage array is coupled to a second storage array controller in the second storage array via a second data communications port.

10. The system of claim 7 wherein the DRAM in the NVRAM storage device in the first storage array includes one or more non-volatile dual in-line memory modules (‘

NVDIMMs’

).

11. The system of claim 7 wherein the backup power source includes a supercapacitor.

12. The system of claim 7 further configured to carry out the step of, responsive to writing the data to the DRAM in the NVRAM storage device in the first storage array, sending an acknowledgment indicating that the data has been written to the first storage array.

13. A non-volatile random access memory (‘

NVRAM’

) storage device for buffering data to be written to an array of non-volatile storage devices, the NVRAM device including;

one or more data communications ports;

one or more dynamic random access memory (‘

DRAM’

) memory modules;

a primary power source configured to provide power to the DRAM memory modules;

a backup power source configured to provide power to the DRAM memory modules upon a failure of the primary power source, wherein the NVRAM storage device is included in a first storage array in a multi-array system, the multi-array system including second storage array that includes a plurality of non-volatile storage devices and an NVRAM storage device in the second storage array, the NVRAM storage device in the second storage array available for exclusive use by one or more storage array controllers in the second storage array; and

an NVRAM controller, the NVRAM controller configured to carry out the steps of;

receiving, from a storage array controller in the first storage array via the one or more data communications ports, an instruction to write data to the one or more DRAM memory modules; and

writing the data to the one or more DRAM memory modules.

14. The NVRAM storage device of claim 13 wherein the NVRAM storage device includes flash memory, and wherein the NVRAM controller is further configured to carry out the steps of:

determining whether the primary power source has failed; and

responsive to determining that the primary power source has failed, initiating a transfer of data contained in the one or more DRAM memory modules to flash memory in the NVRAM storage device.

15. The NVRAM storage device of claim 13 wherein the NVRAM storage device includes a plurality of data communications ports, wherein the NVRAM storage device is coupled to a first storage array controller in the first storage array via a first data communications port and the NVRAM storage device is coupled to a second storage array controller in the first storage array via a second data communications port.

16. The NVRAM storage device of claim 13 wherein the DRAM memory modules in the NVRAM storage device includes one or more non-volatile dual in-line memory modules (‘

NVDIMMs’

).

17. The NVRAM storage device of claim 13 wherein the backup power source includes a supercapacitor.

18. The NVRAM storage device of claim 13 wherein the NVRAM controller is further configured to carry out the step of, responsive to writing the data to the one or more DRAM memory modules, sending an acknowledgment indicating that the data has been written to the array of non-volatile storage devices.