NEURON PERIPHERAL CIRCUITS FOR NEUROMORPHIC SYNAPTIC MEMORY ARRAY BASED ON NEURON MODELS
First Claim
1. A neuromorphic memory system comprising:
- a plurality of neuromorphic memory arrays, each of the neuromorphic memory arrays including rows and columns of neuromorphic memory cells;
a column of postsynaptic circuits, each of the postsynaptic circuits electrically coupled to a plurality of postsynaptic spike timing dependent plasticity (STDP) lines, each of the postsynaptic STDP lines coupled to a row of neuromorphic memory cells at a respective memory array of the memory arrays;
a column of summing circuits, each of the summing circuits electrically coupled to a plurality of postsynaptic leaky integrate and fire (LIF) lines, each of the postsynaptic LIF lines coupled to the row of neuromorphic memory cells at the respective memory array, each of the summing circuits providing a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit of the postsynaptic circuits.
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Accused Products
Abstract
A neuromorphic memory system including neuromorphic memory arrays. Each neuromorphic memory array includes rows and columns of neuromorphic memory cells. A column of postsynaptic circuits is electrically coupled to postsynaptic spike timing dependent plasticity (STDP) lines. Each postsynaptic STDP line is coupled to a row of neuromorphic memory cells. A column of summing circuits is electrically coupled to postsynaptic leaky integrate and fire (LIF) lines. Each postsynaptic LIF line is coupled to the row of neuromorphic memory cells at a respective memory array. Each summing circuit provides a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit.
15 Citations
20 Claims
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1. A neuromorphic memory system comprising:
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a plurality of neuromorphic memory arrays, each of the neuromorphic memory arrays including rows and columns of neuromorphic memory cells; a column of postsynaptic circuits, each of the postsynaptic circuits electrically coupled to a plurality of postsynaptic spike timing dependent plasticity (STDP) lines, each of the postsynaptic STDP lines coupled to a row of neuromorphic memory cells at a respective memory array of the memory arrays; a column of summing circuits, each of the summing circuits electrically coupled to a plurality of postsynaptic leaky integrate and fire (LIF) lines, each of the postsynaptic LIF lines coupled to the row of neuromorphic memory cells at the respective memory array, each of the summing circuits providing a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit of the postsynaptic circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12-19. -19. (canceled)
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20. A neuromorphic memory system comprising:
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a resistive memory cell; a presynaptic neuron circuit configured to generate a presynaptic leaky integrate and fire (LIF) pulse on a presynaptic LIF line at time t1; an access transistor coupled to the presynaptic LIF line, the access transistor activated in response to the presynaptic LIF pulse, the access transistor enabling LIF current to pass through the resistive memory cell to a postsynaptic LIF line; and a postsynaptic neuron circuit including; a LIF capacitor electrically coupled to the postsynaptic LIF line, the LIF capacitor configured to integrate the LIF current at the postsynaptic LIF line over time; a LIF discharge line coupled to the postsynaptic LIF line, the LIF discharge line configured to discharge the LIF capacitor over time; and a LIF comparator electrically coupled to the postsynaptic LIF line, the LIF comparator configured to compare a LIF voltage at the LIF capacitor to a threshold voltage and generate the postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.
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Specification