DISPLAY DEVICE

• US 20160351093A1
• Filed: 05/25/2016
• Published: 12/01/2016
• Est. Priority Date: 05/26/2015
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Yang Wan, Kwak, Won Kyu
• Granted Patent: US 9,928,768 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2203/04106 Multi-sensing digitiser, i.e. digitiser using at least two different sensing technologies simultaneously or alternatively, e.g. for detecting pen and finger, for saving power or for improving position detection
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0202 Addressing of scan or signal lines
• CPC Class Codes: G09G 2310/0232 Special driving of display border areas
• CPC Class Codes: G09G 2330/028 Generation of voltages supplied to electrode drivers in a matrix display other than LCD
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/873 Encapsulations
• CPC Class Codes: H10K 71/70 Testing, e.g. accelerated lifetime tests

Abstract

A display device is disclosed. In one aspect, the device includes a substrate including a display area and a non-display area surrounding the display area and a plurality of pixels formed in the display area. The device also includes a plurality of signal lines formed over the substrate and electrically connected to the pixels and an encapsulation layer formed over the substrate, wherein the signal lines include. The device further includes a plurality of gate lines and a plurality of data lines formed over the substrate and a first crack sensing line electrically connected to a first one of the data lines and overlapping the encapsulation layer in the depth dimension of the display device.

Claims

1. A display device, comprising:

a substrate including a display area and a non-display area surrounding the display area;

a plurality of pixels formed in the display area;

a plurality of signal lines formed over the substrate and electrically connected to the pixels; and

an encapsulation layer formed over the substrate, wherein the signal lines include;

a plurality of gate lines and a plurality of data lines formed over the substrate, and

a first crack sensing line electrically connected to a first one of the data lines and overlapping the encapsulation layer in the depth dimension of the display device.

2. The display device of claim 1, wherein the encapsulation layer is formed in the display area and the non-display area, and wherein the first crack sensing line is formed in the non-display area.

3. The display device of claim 2, further comprising a touch layer including a touch wire and formed over the encapsulation portion, wherein the first crack sensing line is formed on the same layer as the touch wire of the touch layer.

4. The display device of claim 3, wherein the signal lines further include a first signal line and a second signal line formed in the non-display area,

wherein the first crack sensing line is electrically connected to the first data line and extends along an edge of the display area substantially in a semi-circular shape, and

wherein the data lines are electrically connected to the first signal line via a first transistor and the second signal line via a second transistor.

5. The display device of claim 4, wherein the first crack sensing line is electrically connected to the second signal line and the second transistor.

6. The display device of claim 5, further comprising:

a first gate line formed in the non-display area and electrically connected to the first transistor; and

a second gate line electrically connected to the second transistor,

wherein the data lines are configured to receive a first signal from the first signal line based on a first gate-on voltage applied to the first gate line, and

wherein the data lines are configured to receive a second signal from the second signal line based on a second gate-on voltage applied to the second gate line.

7. The display device of claim 6, wherein the second gate-on voltage is configured to be applied after the first gate-on voltage is applied, and wherein the first and second signals are different.

8. The display device of claim 3, further comprising a second crack sensing line electrically connected to a second one of the data lines, wherein the second crack sensing line is formed in the non-display area and does not overlap the encapsulation layer in the depth dimension of the display device.

9. The display device of claim 8, wherein the second crack sensing line is formed on the same layer as the gate lines.

10. The display device of claim 9, further comprising an insulating layer having a contact hole and interposed between the second crack sensing line and the gate lines, wherein the second crack sensing line is connected to the second data line via the contact hole.

11. The display device of claim 10, wherein the signal lines further include a first signal line and a second signal line formed in the non-display area,

wherein the first crack sensing line is electrically connected to the first data line and extends along an edge of the display area substantially in a semi-circle shape,

wherein the second crack sensing line extends along the edge of the display area substantially in parallel with the first crack sensing line, and

wherein the data lines is electrically connected to the first signal line via a first transistor and the second signal line via a second transistor.

12. The display device of claim 11, wherein the first crack sensing line is electrically connected to the second signal line and the second transistor, and wherein the second crack sensing line is electrically connected to the second signal line and the second transistor.

13. The display device of claim 12, further comprising:

a first gate line formed in the non-display area and electrically connected to the first transistor; and

a second gate line electrically connected to the second transistor,

wherein the data lines are configured to receive a first signal from the first signal line based on a first gate-on voltage applied to the first gate line, and

wherein the data lines are configured to receive a second signal from the second signal line based on a second gate-on voltage applied to the second gate line.

14. The display device of claim 13, wherein the second gate-on voltage is configured to be applied after the first gate-on voltage is applied, and wherein the first and second signals are different.

15. The display device of claim 8, wherein the second crack sensing line is formed on the same layer as the gate lines.

16. The display device of claim 15, wherein the signal lines further include a first signal line and a second signal line formed in the non-display area of the substrate,

wherein the first crack sensing line is electrically connected to the first data line and extends along an edge of the display area in a semi-circular shape,

wherein the second crack sensing line extends along the edge of the display area substantially in parallel with the first crack sensing line, and

wherein the data lines is electrically connected to the first signal line via a first transistor and the second signal line via a second transistor.

17. The display device of claim 16, wherein the first crack sensing line is electrically connected to the second signal line and the second transistor, and wherein the second crack sensing line is electrically connected to the second signal line and the second transistor.

18. The display device of claim 17, further comprising:

a first gate line formed in the non-display area of the substrate and electrically connected to the first transistor; and

a second gate line electrically connected to the second transistor,

wherein the data lines are configured to receive a first signal from the first signal line based on a first gate-on voltage applied to the first gate line, and

wherein the data lines are configured to receive a second signal from the second signal line based on a second gate-on voltage applied to the second gate line.

19. The display device of claim 18, wherein the second gate-on voltage is configured to be applied after the first gate-on voltage is applied, and wherein the first and second signals include different signals.

20. The display device of claim 1, further comprising a touch layer including a touch wire and formed over the encapsulation layer, wherein the first crack sensing line is formed in the same layer as the touch wire.

21. A display device, comprising:

a substrate including a display area and a non-display area surrounding the display area;

a plurality of pixels formed in the display area;

an encapsulation layer formed over the substrate;

a plurality of data lines formed over the substrate; and

a first crack sensing line formed in the non-display area and electrically connected to a first one of the data lines, wherein the first crack sensing line overlaps the encapsulation layer in the depth dimension of the display device.

22. The display device of claim 21, further comprising a second crack sensing line electrically connected to a second one of the data lines, wherein the second crack sensing line is formed in the non-display area and does not overlap the encapsulation layer in the depth dimension of the display device.

23. The display device of claim 22, wherein the second crack sensing line is farther from the first crack sensing line than the encapsulation layer.