RECEPTION CIRCUIT, METHOD FOR ADJUSTING TIMING IN RECEPTION CIRCUIT, AND SEMICONDUCTOR DEVICE

• US 20160351245A1
• Filed: 05/20/2016
• Published: 12/01/2016
• Est. Priority Date: 05/28/2015
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: KANO, Hiroyuki, Aoshima, Takanori, Ukai, Hiroaki, Kojima, Kazumi
• Granted Patent: US 9,620,196 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

A reception circuit includes a control signal generation circuit that generates a first enable signal based on a strobe signal and a second enable signal based on a core clock signal and a pointer control signal. A pattern data generation circuit generates determination pattern data from the first enable signal. An asynchronous transfer circuit latches the determination pattern data based on the first enable signal and the strobe signal and outputs determination data corresponding to the latched determination pattern data based on the second enable signal and the core clock signal. A determination circuit determines a timing for generating the pointer control signal based on the determination data. A set value calculation circuit calculates a transfer set value based on the determination result of the determination circuit. The control signal generation circuit updates the pointer control signal based on the transfer set value.

Claims

1. A reception circuit comprising:

a control signal generation circuit that generates

a first enable signal based on a strobe signal,

a pointer control signal based on a read control signal, a transfer set value, and a core clock signal, and

a second enable signal based on the pointer control signal and the core clock signal;

a first asynchronous transfer circuit that latches reception data based on the first enable signal and the strobe signal and outputs output data corresponding to the latched reception data based on the second enable signal and the core clock signal;

a pattern data generation circuit that generates determination pattern data from the first enable signal and inverts a logic of the determination pattern data in accordance with a change in the first enable signal;

a second asynchronous transfer circuit that latches the determination pattern data based on the first enable signal and the strobe signal and outputs determination data corresponding to the latched determination pattern data based on the second enable signal and the core clock signal;

a determination circuit that determines a timing for generating the pointer control signal based on the determination data output from the second asynchronous transfer circuit; and

a set value calculation circuit that calculates the transfer set value based on a determination result of the determination circuit.

2. The reception circuit according to claim 1, further comprising a latency compensation circuit that outputs read data by delaying the output data of the first asynchronous transfer circuit based on a latency set value, wherein the set value calculation circuit calculates the latency set value based on the transfer set value.

3. The reception circuit according to claim 1, wherein the determination circuit generates expected value data based on the second enable signal and determines the timing for generating the pointer control signal by comparing the expected value data with the determination data output from the second asynchronous transfer circuit.

4. The reception circuit according to claim 1, wherein:

the first enable signal generated by the control signal generation circuit includes

a positive phase enable signal that is generated based on the strobe signal, and

a negative phase enable signal that is generated based on an inverse strobe signal having an inverse logic of the strobe signal;

the pattern data generation circuit generates first determination pattern data based on the positive phase enable signal and second determination pattern data based on the negative phase enable signal;

the second asynchronous transfer circuit outputs first determination data and second determination data by transferring the first determination pattern data and the second determination pattern data, respectively;

the determination circuit generates expected value data based on the second enable signal, generates a first determination signal by comparing the first determination data with the expected value data, and generates a second determination signal by comparing the second determination data with the expected value data; and

the set value calculation circuit calculates the transfer set value based on the first determination signal and the second determination signal.

5. The reception circuit according to claim 1, wherein:

the control signal generation circuit generates, based on the transfer set value, a fast enable signal changing at an earlier timing than the second enable signal and a slow enable signal changing at a later timing than the second enable signal;

the first asynchronous transfer circuit includes

a first latch circuit that latches the reception data based on the first enable signal, and

a second latch circuit that latches an output signal of the first latch circuit based on the second enable to outputs the output data;

the second asynchronous transfer circuit includes

a third latch circuit that latches the determination pattern data based on the first enable signal,

a fourth latch circuit that latches an output signal of the third latch circuit based on the fast enable signal, and

a fifth latch circuit that latches the output signal of the third latch circuit based on the slow enable signal;

the determination circuit includes

a first determination circuit that generates first expected value data based on the fast enable signal and compares the first expected value data with an output signal of the fourth latch circuit to determine a timing of the fast enable signal, and

a second determination circuit that generates second expected value data based on the slow enable signal and compares the second expected value data with an output signal of the fifth latch circuit to determine a timing of the slow enable signal; and

the set value calculation circuit calculates the transfer set value based on a determination result of the first determination circuit and a determination result of the second determination circuit.

6. A method for adjusting a timing in a reception circuit, the method comprising:

generating a first enable signal based on a strobe signal;

generating a pointer control signal based on a read control signal, a transfer set value, and a core clock signal;

generating a second enable signal based on the pointer control signal and the core clock signal, wherein the reception circuit latches reception data based on the first enable signal and the strobe signal and outputs output data corresponding to the latched reception data based on the second enable signal and the core clock signal;

generating determination pattern data from the first enable signal, wherein the generating determination pattern data includes inverting a logic of the determination pattern data in accordance with a change in the first enable signal;

latching the determination pattern data based on the first enable signal and the strobe signal;

outputting determination data corresponding to the latched determination pattern data based on the second enable signal and the core clock signal;

determining a timing for generating the pointer control signal based on the determination data to generate a determination signal;

updating the transfer set value based on the determination signal; and

updating the pointer control signal based on the updated transfer set value to adjust a timing for changing a domain from the strobe signal to the core clock signal.

7. A semiconductor device comprising:

a memory controller that generates a read control signal to control access to a memory; and

a reception circuit that delays a strobe signal output from the memory to generate a delay strobe signal and transfers read data to the memory controller by retrieving reception data from the memory based on the delay strobe signal and a core clock signal, wherein

the reception circuit includes a control signal generation circuit that generates

a first enable signal based on the delay strobe signal,

a pointer control signal based on the read control signal, a transfer set value, and the core clock signal, and

a second enable signal based on the pointer control signal and the core clock signal,

a first asynchronous transfer circuit that latches the reception data based on the first enable signal and the delay strobe signal and outputs output data corresponding to the latched reception data based on the second enable signal and the core clock signal,

a pattern data generation circuit that generates determination pattern data from the first enable signal and inverts a logic of the determination pattern data in accordance with a change in the first enable signal,

a second asynchronous transfer circuit that latches the determination pattern data based on the first enable signal and the delay strobe signal and outputs determination data corresponding to the latched determination pattern data based on the second enable signal and the core clock signal,

a determination circuit that determines a timing for generating the pointer control signal based on the determination data output from the second asynchronous transfer circuit, and

a set value calculation circuit that calculates the transfer set value based on a determination result of the determination circuit.