Multiple Junction Thin Film Transistor

• US 20160351722A1
• Filed: 05/27/2015
• Published: 12/01/2016
• Est. Priority Date: 05/27/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Zhou, Guangle, Wu, Ming-Che, Chen, Yung-Tin
• Granted Patent: US 9,653,617 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices

Abstract

A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p− region of the body. The TFT may have an n+ source and an n+ drain on either side of the p− region of the body. Thus, the TFT has an n+/p−/n+/p−/n+ structure in this example. The n+ layer in the p− region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p− body and/or thickness of the n+ layer in the p− body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n− region of the body. The TFT may have a p+ source and a p+ drain on either side of the p− region of the body.

Claims

1. A semiconductor device, comprising:

a substrate having a major surface;

a first conductive region;

a second conductive region;

a thin film transistor comprising;

i) a first source/drain having a first type of conductivity, wherein the first source/drain is electrically connected to the first conductive region;

ii) a second source/drain having the first type of conductivity, wherein the second source/drain is electrically connected to the second conductive region;

iii) a body between the first source/drain and the second source/drain, wherein the body comprises a first body region having a second type of conductivity that is opposite first type of conductivity, a second body region having the first type of conductivity, and a third body region having the second type of conductivity, wherein the second body region is between the first body region and the third body region, wherein the second body region has a thickness as measured between the first body region and the third body region in the range between 50 to 120 nanometers, wherein a peak doping concentration of the second body region is greater than a peak doping concentration of the first body region and is greater than a peak doping concentration of the third body region, wherein the first source/drain, the body, and the second source/drain are aligned with each other vertically with respect to the major surface of the substrate; and

;

iv) a control gate adjacent to the body; and

a management circuit coupled to the control gate, wherein the management circuit is configured to apply a first signal to the control gate to electrically connect the first conductive region to the second conductive region and to apply a second signal to the control gate to electrically disconnect the first conductive region from the second conductive region.

2. The semiconductor device of claim 1, wherein the first body region and the third body region are p−

, wherein the second body region is n+, wherein the first source/drain is n+ and wherein the second source/drain is n+.

4. The semiconductor device of claim 1, wherein the first body region and the third body region are n−

, wherein the second body region is p+.

5. The semiconductor device of claim 1, wherein the second conductive region is a bit line that is oriented vertically with respect to the major surface of the substrate, wherein the first conductive region is a global bit line.

7. The semiconductor device of claim 1, further comprising:

a plurality of non-volatile memory cells in a three-dimensional memory array, wherein the second conductive region is electrically connected to the plurality of non-volatile memory cells.

22. The semiconductor device of claim 1, wherein the second body region has a thickness of approximately 50 nanometers.

23. The semiconductor device of claim 1, wherein the second body region has a thickness as measured from the first body region to the third body region configured to achieve a target breakdown voltage for the thin film transistor.

24. The semiconductor device of claim 23, wherein the peak doping concentration of the second body region is configured to control the breakdown voltage of the thin film transistor.

27. The semiconductor device of claim 1, wherein the thickness of the second body region as measured from the first body region to the third body region is configured to meet a target drain current (I_D) versus drain-to-source voltage (Vds) curve for the thin film transistor.

28. The semiconductor device of claim 1, wherein the thickness of the second body region as measured from the first body region to the third body region is configured to meet a target transconductance (g_m) versus gate-to-source voltage (Vgs) curve for the thin film transistor.

30. The semiconductor device of claim 1, wherein the second body region has a thickness as measured between the first body region and the third body region of between 50 to 80 nanometers.

31. The semiconductor device of claim 1, wherein the second body region has a thickness as measured between the first body region and the third body region of between 80 to 120 nanometers.

3. (canceled)

6. (canceled)

8-14. -14. (canceled)

15. A semiconductor device, comprising:

a semiconductor substrate having a major surface that extends in a horizontal plane;

a first conductive line;

a second conductive line that extends in a vertical direction with respect to the horizontal plane;

a thin film transistor comprising;

a) a first semiconductor layer having a first peak doping concentration of a first type of conductivity, wherein the first semiconductor layer is electrically connected to the first conductive line;

b) a second semiconductor layer having a second peak doping concentration of a second type of conductivity that is opposite the first type of conductivity;

c) a third semiconductor layer having a third peak doping concentration of the first type of conductivity, wherein the third semiconductor layer has a thickness of between 50 to 120 nanometers;

d) a fourth semiconductor layer having a fourth peak doping concentration of the second type of conductivity;

e) a fifth semiconductor layer having a fifth peak doping concentration of the first type of conductivity, wherein the fifth semiconductor layer is electrically connected to the second conductive line, wherein the first, second, third, fourth, and fifth semiconductor layers form a stack that extends in the vertical direction, wherein the first, third and fifth peak doping concentrations are each at least 10 times greater than the second peak doping concentration and at least 10 times greater than the fourth peak doping concentration;

f) a conductive control gate adjacent to the second, third, and fourth semiconductor layers; and

g) a tunnel dielectric between the conductive control gate and the second, third, and fourth semiconductor layers.

16. The semiconductor device of claim 15, further comprising:

a plurality of word lines; and

a plurality of reversible resistivity memory cells each having a first end in electrical contact with the second conductive line and a second end in electrical contact with one of the word lines.

17. The semiconductor device of claim 15, wherein the first semiconductor layer is n+, the second semiconductor layer is p−

, the third semiconductor layer is n+, the fourth semiconductor layer is p−

, and the fifth semiconductor layer is n+.

18. The semiconductor device of claim 15, wherein the first, third and fifth peak doping concentrations are each at least 100 times greater than the second peak doping concentration and at least 100 times greater than the fourth peak doping concentration.

19. The semiconductor device of claim 15, wherein the first, third and fifth peak doping concentrations are each at least 1000 times greater than the second peak doping concentration and at least 1000 times greater than the fourth peak doping concentration.

20. A non-volatile storage system, comprising:

a semiconductor substrate having a major surface;

a three dimensional memory array of memory cells above the semiconductor substrate;

a plurality of word lines coupled to the memory cells;

a plurality of global bit lines;

a plurality of vertical bit lines electrically connected to the memory cells, wherein the vertical bit lines are vertically oriented with respect to the major surface of the semiconductor substrate; and

a plurality of vertically oriented thin film transistor (TFT) select devices that are above the semiconductor substrate, wherein the vertically oriented TFT select devices reside between the vertical bit lines and the global bit lines;

each of the vertically oriented TFT select devices comprising;

a source having a first type of conductivity, wherein the source is electrically connected to a first of the global bit lines;

a drain having the first type of conductivity, wherein the drain is electrically connected to a first of the vertical bit lines;

a body between the source and the drain, wherein the body comprises a first region having a second type of conductivity that is opposite first type of conductivity, a second region having the first type of conductivity, and a third region having the second type of conductivity, wherein the second region is between the first region and the third region, wherein a peak doping concentration of the second region is greater than a peak doping concentration of the first region and is greater than a peak doping concentration of the third region, wherein the second body region has a thickness in the range of 50 to 120 nanometers, wherein the source, the body, and the drain are aligned with each other vertically with respect to the major surface of the semiconductor substrate; and

a control gate adjacent to the body.

21. A semiconductor device, comprising:

a substrate having a major surface;

a first conductive region;

a second conductive region;

a thin film transistor comprising;

i) a first source/drain having a first type of conductivity, wherein the first source/drain is electrically connected to the first conductive region;

ii) a second source/drain having the first type of conductivity, wherein the second source/drain is electrically connected to the second conductive region;

iii) a body between the first source/drain and the second source/drain, wherein the body comprises a first body region having a second type of conductivity that is opposite first type of conductivity, a second body region having the first type of conductivity, and a third body region having the second type of conductivity, wherein the second body region is between the first body region and the third body region, wherein the second body region has a thickness as measured from the first body region to the third body region in the range of 50 to 120 nanometers, wherein a peak doping concentration of the second body region is greater than a peak doping concentration of the first body region and is greater than a peak doping concentration of the third body region, wherein the first source/drain, the body, and the second source/drain are aligned with each other vertically with respect to the major surface of the substrate; and

iv) a control gate adjacent to the body; and

means for applying a first signal to the control gate to electrically connect the first conductive region to the second conductive region and to apply a second signal to the control gate to electrically disconnect the first conductive region from the second conductive region.

25-26. -26. (canceled)

29. (canceled)

32. A method of forming a semiconductor device, comprising:

forming a first conductive line above a semiconductor substrate having a major surface that extends in a horizontal plane;

forming a thin film transistor comprising;

i) forming a first semiconductor layer having a first peak doping concentration of a first type of conductivity, including forming the first semiconductor layer in electrical contact with the first conductive line;

ii) forming a second semiconductor layer having a second peak doping concentration of a second type of conductivity that is opposite the first type of conductivity;

iii) forming a third semiconductor layer having a third peak doping concentration of the first type of conductivity, wherein the third semiconductor layer has a thickness of between 50 to 120 nanometers;

iv) forming a fourth semiconductor layer having a fourth peak doping concentration of the second type of conductivity;

v) forming a fifth semiconductor layer having a fifth peak doping concentration of the first type of conductivity, wherein the first, second, third, fourth, and fifth semiconductor layers form a stack that extends in the vertical direction, wherein the first, third and fifth peak doping concentrations are each at least 10 times greater than the second peak doping concentration and at least 10 times greater than the fourth peak doping concentration;

vi) forming a tunnel dielectric as a conformal layer on the first, second, third, fourth, and fifth semiconductor layers; and

vii) forming a conductive control gate adjacent to the second, third, and fourth semiconductor layers, wherein the tunnel dielectric is between the conductive control gate and the second, third, and fourth semiconductor layers; and

forming a second conductive line that extends in a vertical direction with respect to the horizontal plane, including forming the second conductive line in electrical contact with the fifth semiconductor layer.