CROSSTALK REDUCTION IN MULTIPLEXERS

• US 20160352387A1
• Filed: 06/01/2015
• Published: 12/01/2016
• Est. Priority Date: 06/01/2015
• Status: Active Grant

• Current Assignee: Diodes Incorporated
• Original Assignee: Pericom Semiconductor Corporation (Diodes Incorporated)
• Inventors: Yeung, Tony, Zhang, Michael Y.
• Granted Patent: US 9,762,287 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating

Abstract

Multiplexers are described in which differential signals on the signal paths associated with unselected differential inputs are converted to common mode signals to reduce crosstalk between unselected signal paths and the multiplexer'"'"'s active signal path.

Claims

1. A multiplexer, comprising:

a plurality of multiplexer inputs, each of the multiplexer inputs being a differential input;

a multiplexer output, the multiplexer output being a differential output;

selection circuitry configured to enable an active signal path from a selected one of the multiplexer inputs to the multiplexer output, the selection circuitry also being configured to disable unselected signal paths corresponding to unselected ones of the multiplexer inputs; and

conversion circuitry configured to convert, for each of the unselected signal paths, a corresponding differential signal to a common mode signal.

2. The multiplexer of claim 1, wherein the conversion circuitry comprises a plurality of switches, each of the switches being configured to convert the differential signal for a corresponding one of the unselected signal paths by connecting complementary circuit nodes of the corresponding unselected signal path.

3. The multiplexer of claim 2, wherein each of the multiplexer inputs has an inverting node and a non-inverting node, and wherein the complementary circuit nodes of each unselected signal path correspond to the inverting and non-inverting nodes of the corresponding multiplexer input.

4. The multiplexer of claim 2, wherein each of the multiplexer inputs has an inverting node and a non-inverting node, and wherein the complementary circuit nodes of each unselected signal path correspond to internal circuit nodes of the multiplexer subsequent to the inverting and non-inverting nodes of the corresponding multiplexer input and before the selection circuitry.

5. The multiplexer of claim 1, further comprising a plurality of isolation circuits, each isolation circuit being associated with a corresponding one of the signal paths and being configured to isolate the corresponding multiplexer input from the common mode signal.

6. The multiplexer of claim 1, wherein the multiplexer is an active multiplexer or a passive multiplexer.

7. The multiplexer of claim 1, wherein the conversion circuitry comprises a plurality of active devices, each of the active devices having a high input impedance and being configured to convert the differential signal for a corresponding one of the unselected signal paths by combining complementary signals on complementary circuit nodes of the corresponding unselected signal path.

8. The multiplexer of claim 7, wherein each of the multiplexer inputs has an inverting node and a non-inverting node, and wherein the complementary circuit nodes of each unselected signal path correspond to the inverting and non-inverting nodes of the corresponding multiplexer input.

9. The multiplexer of claim 7, wherein each of the multiplexer inputs has an inverting node and a non-inverting node, and wherein the complementary circuit nodes of each unselected signal path correspond to internal circuit nodes of the multiplexer subsequent to the inverting and non-inverting nodes of the corresponding multiplexer input and before the selection circuitry.

10. The multiplexer of claim 7, wherein each of the active devices comprises an analog amplifier configured to be bypassed or disabled when the corresponding multiplexer input is the selected multiplexer input.

11. A device configured to connect one or more host devices with a plurality of target devices, the device comprising one or more instances of the multiplexer of claim 1.

12. The device of claim 11, wherein the device is a serial data interface configured to transmit communications among the host and target devices using a single serial data protocol.

13. The device of claim 11, wherein the device is a serial data interface configured to transmit communications among the host and target devices using multiple serial data protocols.

14. The device of claim 11, wherein the device is a controller configured to communicate with the host and target devices using multiple serial data protocols.

15. The device of claim 11, wherein the device is a converter configured to convert communications among the host and target devices between first and second serial data protocols.

16. A multiplexer, comprising:

a plurality of multiplexer inputs, each of the multiplexer inputs being a differential input;

a multiplexer output, the multiplexer output being a differential output;

selection circuitry configured to enable an active signal path from a selected one of the multiplexer inputs to the multiplexer output, the selection circuitry also being configured to disable unselected signal paths corresponding to unselected ones of the multiplexer inputs; and

a plurality of active devices, each of the active devices having a high input impedance and being configured to combine complementary signals on complementary circuit nodes of a corresponding one of the unselected signal paths.

17. The multiplexer of claim 16, wherein each of the multiplexer inputs has an inverting node and a non-inverting node, and wherein the complementary circuit nodes of each unselected signal path correspond to the inverting and non-inverting nodes of the corresponding multiplexer input.

18. The multiplexer of claim 16, wherein each of the multiplexer inputs has an inverting node and a non-inverting node, and wherein the complementary circuit nodes of each unselected signal path correspond to internal circuit nodes of the multiplexer subsequent to the inverting and non-inverting nodes of the corresponding multiplexer input and before the selection circuitry.

19. The multiplexer of claim 16, wherein each of the active devices comprises an analog amplifier configured to be bypassed or disabled when the corresponding multiplexer input is the selected multiplexer input.

20. A multiplexer, comprising:

a plurality of multiplexer inputs, each of the multiplexer inputs being a differential input;

a multiplexer output, the multiplexer output being a differential output;

selection circuitry configured to enable an active signal path from a selected one of the multiplexer inputs to the multiplexer output, the selection circuitry also being configured to disable unselected signal paths corresponding to unselected ones of the multiplexer inputs;

a plurality of switches, each of the switches being configured to connect complementary circuit nodes of a corresponding one of the unselected signal paths; and

a plurality of isolation circuits, each isolation circuit being associated with a corresponding one of the signal paths and being configured to isolate the corresponding multiplexer input from the common mode signal.

21. The multiplexer of claim 20, wherein each of the multiplexer inputs has an inverting node and a non-inverting node, and wherein the complementary circuit nodes of each unselected signal path correspond to the inverting and non-inverting nodes of the corresponding multiplexer input.

22. The multiplexer of claim 20, wherein each of the multiplexer inputs has an inverting node and a non-inverting node, and wherein the complementary circuit nodes of each unselected signal path correspond to internal circuit nodes of the multiplexer subsequent to the inverting and non-inverting nodes of the corresponding multiplexer input and before the selection circuitry.