Array Substrate And Manufacturing Method For The Same, And Totally Reflective Type Liquid Crystal Display

• US 20160357044A1
• Filed: 05/22/2015
• Published: 12/08/2016
• Est. Priority Date: 12/10/2014
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Lv, Zhijun, Li, Tailiang, Gao, Tao, Ning, Ce, Sun, Shuang
• Application Number:
  US14/891,729
• Publication Number:
  US 20160357044A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133553 Reflecting elements associated to illuminating devices G02F1/133605
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2203/02 reflective
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

The present disclosure discloses an array substrate, comprising a substrate, a plurality of pixel regions on the substrate, and a thin-film transistor formed in each of the pixel regions, each of the pixel regions comprising a pixel electrode region, wherein, the thin-film transistor comprises a gate layer and a source/drain layer formed laminatedly on the substrate; the array substrate further comprises a flat layer and a reflective metal layer formed in sequence on the substrate and covering at least the pixel electrode region and the thin-film transistor; the reflective metal layer is electrically connected to a drain of the thin-film transistor; and at least one of the gate layer and the source/drain layer is formed of a single metal layer. The present disclosure further provides a method for manufacturing the array substrate and a totally reflective type liquid crystal display comprising the array substrate.

Claims

1. An array substrate, comprising a substrate, a plurality of pixel regions on the substrate, and a thin-film transistor formed in each of the pixel regions, each of the pixel regions comprising a pixel electrode region, wherein,

the thin-film transistor comprises a gate layer and a source/drain layer formed laminatedly on the substrate;

the array substrate further comprises a flat layer and a reflective metal layer formed in sequence on the substrate and covering at least the pixel electrode region and the thin-film transistor;

the reflective metal layer is electrically connected to a drain of the thin-film transistor; and

at least one of the gate layer and the source/drain layer is formed of a single metal layer.

2. The array substrate of claim 1, wherein the gate layer and the source/drain layer both are formed of a single metal layer.

3. The array substrate of claim 2, wherein the gate layer and the source/drain layer are formed of one and the same metal.

4. The array substrate of claim 3, wherein the gate layer and the source/drain layer have the same thickness.

5. The array substrate of claim 3, wherein the metal comprises one of molybdenum, copper and aluminum.

6. The array substrate of claim 4, wherein the gate layer and the source/drain layer both are formed of a molybdenum layer with a thickness of 2200 Å

.

7. The array substrate of claim 1, wherein a portion of the reflective metal layer covering the pixel electrode region is substantially flat, and the reflective metal layer is formed of one of Al, Ag and AlNd.

9. The array substrate of claim 1, wherein the flat layer comprises a resin layer.

10. The array substrate of claim 1, further comprising a surrounding lead wire region, wherein

the reflective metal layer is further formed on the surrounding lead wire region;

and

a portion of the reflective metal layer located on the surrounding lead wire region is covered with an indium tin oxide layer.

11. A totally reflective type liquid crystal display, comprising an array substrate of claim 1.

22. A totally reflective type liquid crystal display, comprising an array substrate of claim 9.

8. (canceled)

12. A method for manufacturing an array substrate, comprising:

providing a substrate comprising a plurality of pixel regions which is to form a plurality of pixels, each of the pixel regions comprising a pixel electrode region which is to form a pixel electrode;

forming a thin-film transistor in the pixel region, wherein the thin-film transistor comprises a gate layer and a source/drain layer formed laminatedly on the substrate, and at least one of the gate layer and the source/drain layer is formed of a single metal layer; and

forming a flat layer and a reflective metal layer, which cover at least the pixel electrode region and the thin-film transistor, in sequence on the substrate, wherein the reflective metal layer is configured to be electrically connected to a drain of the thin-film transistor.

13. The method of claim 12, wherein the gate layer and the source/drain layer both are formed of a single metal layer.

14. The method of claim 13, wherein the gate layer and the source/drain layer are formed of one and the same metal.

15. The method of claim 14, wherein the gate layer and the source/drain layer have the same thickness.

16. The method of claim 14, wherein the metal comprises one of molybdenum, copper and aluminum.

17. The method of claim 15, wherein the gate layer and the source/drain layer both are formed of a molybdenum layer with a thickness of 2200 Å

.

18. The method of claim 12, wherein a portion of the reflective metal layer covering the pixel electrode region is substantially flat, and the reflective metal layer is formed of one of Al, Ag and AlNd.

19. The method of claim 18, wherein the reflective metal layer is formed of one of Al, Ag and AlNd.

20. The method of claim 12, wherein the flat layer comprises a resin layer.

21. The method of claim 12, wherein the substrate further comprises a surrounding lead wire region, wherein the reflective metal layer is further formed on the surrounding lead wire region;

the method further comprises;

forming an indium tin oxide layer, which covers a portion of the reflective metal layer located on the surrounding lead wire region, on the substrate.