MEMORY DEVICE THAT DIVIDES WRITE DATA INTO A PLURALITY OF DATA PORTIONS FOR DATA WRITING

• US 20160357456A1
• Filed: 03/07/2016
• Published: 12/08/2016
• Est. Priority Date: 06/03/2015
• Status: Abandoned Application

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iwasaki, Kiyotaka
• Application Number:
  US15/063,431
• Publication Number:
  US 20160357456A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory device includes a nonvolatile memory unit including a plurality of banks, and a memory controller. The memory controller is configured to divide write data received from a host into a plurality of data portions, and with respect to each of the data portions, determine a bank in which said data portion is to be written and generate a write command to write said data portion to the determined bank. The memory controller determines the bank in which each of the data portions is to be written, based on the number of write commands queued for each of the banks.

Claims

1. A memory device, comprising:

a nonvolatile memory unit including a plurality of banks; and

a memory controller configured to

divide write data received from a host into a plurality of data portions, and

with respect to each of the data portions, determine a bank in which said data portion is to be written and generate a write command to write said data portion to the determined bank, wherein

the memory controller determines the bank in which each of the data portions is to be written, based on the number of write commands queued for each of the banks.

2. The memory device according to claim 1, wherein

the memory controller includes a counter configured to count the number of write commands queued for each of the banks.

3. The memory device according to claim 2, wherein

the counter is configured to increment the number of write commands queued for a bank when the memory controller generates a write command to write a data portion in said bank, and decrement the number of write commands queued for a bank when a data portion has been written in said bank.

4. The memory device according to claim 1, wherein

the memory controller determines a bank for which the smallest number of write commands are queued to be the bank in which a data portion is to be written.

5. The memory device according to claim 1, wherein

the data portions includes first and second data portions, and

the memory controller determines the bank in which the first data portion is to be written, prior to determining the bank in which the second data portion is to be written.

6. The memory device according to claim 1, wherein

the memory controller determines the bank in which each of the data portions is to be written, further based on remaining capacity of each bank.

7. The memory device according to claim 6, wherein

the memory controller includes a table indicating the remaining capacity of each bank.

8. The memory device according to claim 1, wherein

the memory controller is configured to determine a plurality of candidate banks, based on remaining capacity of each bank, and determines the bank in which each of the data portions is to be written, from the candidate banks.

9. The memory device according to claim 1, wherein

the memory controller is further configured to generate parity data with respect to each of the data portions and append corresponding parity data to each of the data portions.

10. The memory device according to claim 1, wherein

the nonvolatile memory unit includes a NAND memory unit, and

each of the banks includes a plurality of multi-level memory cells.

11. A method for storing write data received from a host in a plurality of banks of a nonvolatile memory, the method comprising:

dividing the write data into a plurality of data portions; and

with respect to each of the data portions, determining a bank in which said data portion is to be written and generating a write command to write said data portion to the determined bank, wherein

the bank in which each of the data portions is to be written is determined based on the number of write commands queued for each of the banks.

12. The method according to claim 11, further comprising:

counting the number of write commands queued for each of the banks.

13. The method according to claim 12, wherein the counting includes

incrementing the number of write commands queued for a bank when a write command to write a data portion in said bank is generated, and

decrementing the number of write commands queued for a bank when a data portion has been written in said bank.

14. The method according to claim 11, wherein

the bank in which each of the data portions is to be written is determined further based on remaining capacity of each bank.

15. The method according to claim 11, further comprising:

determining a plurality of candidate banks, based on remaining capacity of each bank, wherein

the bank in which each of the data portions is to be written is determined from the candidate banks.

16. A memory device, comprising:

a nonvolatile memory unit including a plurality of banks; and

a memory controller configured to

divide write data received from a host into a plurality of data portions, and

with respect to each of the data portions, determine a bank in which said data portion is to be written and write each of the data portions in the determined bank, wherein

the memory controller determines the bank in which each of the data portions is to be written, based on a queue delay of each of the banks.

17. The memory device according to claim 16, wherein

the data portions includes first and second data portions, and

the memory controller determines the bank in which the first data portion is to be written, prior to determining the bank in which the second data portion is to be written.

18. The memory device according to claim 16, wherein

the memory controller determines the bank in which each of the data portions is to be written, also based on remaining capacity of each bank.

19. The memory device according to claim 16, wherein

the memory controller is configured to determine a plurality of candidate banks, based on remaining capacity of each bank, and determines the bank in which each of the data portions is to be written, from the candidate banks.

20. The memory device according to claim 16, wherein

the nonvolatile memory unit includes a NAND memory unit, and

each of the banks includes a plurality of multi-level memory cells.