SEMICONDUCTOR MEMORY DEVICE PROVIDING ANALYSIS AND CORRECTING OF SOFT DATA FAIL IN STACKED CHIPS

• US 20160357630A1
• Filed: 05/02/2016
• Published: 12/08/2016
• Est. Priority Date: 06/05/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, DongHun, HA, Kyoung-nam, KIM, Hyungdong, JUNG, Jun-Phil
• Granted Patent: US 10,580,719 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

The semiconductor memory device includes first group dies including at least one buffer die, and second group dies including a plurality of memory dies stacked on the first group dies and conveying data through a plurality of TSV lines. Here, at least one of the plurality of memory dies includes a first type ECC circuit which generates transmission parity bits using transmission data to be transmitted to the first group die, and the buffer die includes a second type ECC circuit which corrects, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits and generates error-corrected data.

Claims

1. A semiconductor memory device comprising:

first group dies comprising at least one buffer die; and

second group dies comprising a plurality of memory dies, the plurality of memory dies stacked on the first group dies and conveying data through a plurality of through silicon via (TSV) lines,

wherein at least one of the plurality of memory dies includes a first type error correction coding (ECC) circuit configured to generate transmission parity bits based on transmission data to the first group dies, and

wherein the buffer die includes a second type ECC circuit configured to correct the transmission error using the transmission parity bits when a transmission error occurs in the transmission data received through the plurality of TSV lines.

2. The semiconductor memory device of claim 1, wherein the semiconductor memory device is a stacked memory device configured to convey the data and control signals through the plurality of TSVs lines.

3. The semiconductor memory device of claim 1, wherein the plurality of TSV lines are formed with through silicon vias.

4. The semiconductor memory device of claim 1, wherein the first type ECC circuit is configured to perform error correction on data outputted from the memory dies before sending the transmission data.

5. The semiconductor memory device of claim 1, wherein the transmission error occurring in the transmission data is a soft data fail which occurs due to noise of the plurality of TSV lines.

6. The semiconductor memory device of claim 1, wherein the semiconductor memory device is applied to a 3D chip structure or a 2.5D chip structure.

7. The semiconductor memory device of claim 1, wherein each of the plurality of memory dies comprises DRAM cells.

8. The semiconductor memory device of claim 1, wherein at least one of the plurality of memory dies comprises DRAM cells.

9. The semiconductor memory device of claim 1, wherein the semiconductor memory device is of a 3D chip structure to communicate with a host.

10. The semiconductor memory device of claim 9, wherein the host is connected with the buffer die through a data bus.

11. A semiconductor memory device comprising:

a buffer die on a substrate; and

a plurality of memory dies stacked on the buffer die and transmitting data through a plurality of through silicon via (TSV) lines,

wherein each of the plurality of memory dies includes a first type error correction coding (ECC) circuit configured to generate transmission parity bits based on transmission data to be transmitted to the buffer die, and

wherein the buffer die includes a second type ECC circuit configured to check whether a transmission error occurs in the transmission data received through the plurality of TSV lines and to correct the transmission error based on the transmission parity bits upon detecting transmission error.

12. The semiconductor memory device of claim 11, wherein the TSV lines are through electrodes implemented with through silicon vias.

13. The semiconductor memory device of claim 12, wherein the semiconductor memory device is a stacked memory device in which the butler die and the memory dies are stacked on the substrate and are connected through TSV lines.

14. The semiconductor memory device of claim 11, wherein the transmission error occurring in the transmission data comprises a soft data fail which occurs due to noise of the plurality of TSV lines.

15. The semiconductor memory device of claim 11, wherein the buffer die communicates with a host through a data bus in a 2.5D chip structure.

16. A semiconductor memory device comprising:

first group dies comprising at least one buffer die; and

second group dies comprising a plurality of memory dies which are stacked on the first group dies and conveying data through a plurality of through silicon via (TSV) lines,

wherein at least one of the plurality of memory dies comprises a cell core error correction coding (ECC) circuit which generates transmission parity bits using transmission data to be transmitted to the first group dies, and

wherein the butler die comprises a via ECC circuit which corrects, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits, generates error-corrected data, and sends the error-corrected data to a host.

17. The semiconductor memory device of claim 16, wherein the semiconductor memory device is a stacked memory device configured to conveys the data and control signals through the plurality of TSV lines.

18. The semiconductor memory device of claim 16, wherein the transmission error occurring in the transmission data is a soft data fail which occurs due to noise of the plurality of TSV lines.

19. The semiconductor memory device of claim 16, wherein each of the plurality of memory dies comprises DRAM cells.

20. The semiconductor memory device of claim 16, wherein the cell core ECC circuit is configured to perform error correction on data outputted from the memory dies before the transmission data is sent.