SYSTEM AND METHOD FOR MRAM HAVING CONTROLLED AVERAGABLE AND ISOLATABLE VOLTAGE REFERENCE

• US 20160358649A1
• Filed: 08/23/2016
• Published: 12/08/2016
• Est. Priority Date: 10/21/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Jung Pill, Kim, Taehyun
• Granted Patent: US 9,666,274 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

Claims

1. A method for a Non-Volatile Resistive memory comprising:

providing at least one array of bitcells (I/O), each I/O having at least one reference cell having a reference voltage output node and a corresponding I/O reference line;

selecting at least two of the I/O reference lines for a common reference line; and

coupling at least two of the selected I/O reference lines to form a common reference line.

2. The method of claim 1, wherein the selecting comprises:

comparing a voltage at the respective reference voltage output node of at least two of the I/Os to a given acceptable range; and

selecting at least one of the I/O reference lines based, at least in part, on a result of the comparing.

3. The method of claim 1, further comprising:

identifying an acceptability of a voltage at the reference voltage output of the reference cell of at least one of the I/Os, relative to a given range of acceptability; and

isolating at least one of the reference cells based on a result of the identifying an acceptability.

4. The method of claim 3, wherein at least one of the provided I/Os has a conducting link between the I/O'"'"'s reference voltage output node and I/O reference line, and wherein at least one isolating includes blowing the conducting link.

5. The method of claim 3, wherein at least one of the provided I/Os has a programmable switch between the I/O'"'"'s reference voltage output node and I/O reference line, and wherein at least one isolating includes programming the programmable switch to an open state.

6. A Non-Volatile Resistive bitcell array memory comprising:

means for generating a first reference voltage;

means for generating a second reference voltage;

means for providing a first sensing reference and a second sensing reference, including means for selectively combining the first reference voltage and the second reference voltage into a common voltage and for selectively providing the common voltage as the first sensing reference, and means for selectively providing the first reference voltage as the first sensing reference;

means for sensing a voltage of a first array of bitcells relative to the first sensing reference; and

means for sensing a voltage of a second array of bitcells relative to the second sensing reference.

7. The memory of claim 6, wherein the means for providing the first sensing reference and the second sensing reference further includes means for selectively providing the second reference voltage as the second sensing reference.

8. The memory of claim 6, wherein the means for providing the first sensing reference and the second sensing reference further includes means for selectively providing the first reference voltage as the second sensing reference.

9. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:

select at least two of an array of bitcells (I/O), each I/O having at least one reference cell having a reference voltage output node and a corresponding I/O reference line, for a common reference line; and

couple at least two of the selected I/O reference lines to form a common reference line.

10. The non-transitory computer-readable storage medium of claim 9, further comprising instructions that, when executed by the processor, cause the processor to:

compare a voltage at the respective reference voltage output node of at least two of the I/Os to a given acceptable range; and

select at least one of the I/O reference lines based, at least in part, on a result of the comparison.

11. The non-transitory computer-readable storage medium of claim 9, further comprising instructions that, when executed by the processor, cause the processor to:

identify an acceptability of a voltage at the reference voltage output of the reference cell of at least one of the I/Os, relative to a given range of acceptability; and

isolate at least one of the reference cells based on a result of the identification of the acceptability.

12. The non-transitory computer-readable storage medium of claim 9, wherein at least one of the I/Os has a conducting link between the I/O'"'"'s reference voltage output node and I/O reference line, and wherein at least one isolation includes blowing the conducting link.

13. The non-transitory computer-readable storage medium of claim 9, wherein at least one of the I/Os has a programmable switch between the I/O'"'"'s reference voltage output node and I/O reference line, and wherein at least one isolation includes programming the programmable switch to an open state.