ATOMIC LAYER ETCHING OF GaN AND OTHER III-V MATERIALS

• US 20160358782A1
• Filed: 06/03/2016
• Published: 12/08/2016
• Est. Priority Date: 06/05/2015
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Ohba, Tomihito, Yang, Wenbing, Tan, Samantha, Kanarik, Keren Jacobs, Marks, Jeffrey, Nojiri, Kazuo
• Granted Patent: US 10,056,264 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01J 2237/334 Etching
• CPC Class Codes: H01J 37/321 the radio frequency energy being inductively coupled to the plasma
• CPC Class Codes: H01J 37/32706 Polarising the substrate
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

Provided herein are ALE methods of removing III-V materials such as gallium nitride (GaN) and related apparatus. In some embodiments, the methods involve exposing the III-V material to a chlorine-containing plasma without biasing the substrate to form a modified III-V surface layer; and applying a bias voltage to the substrate while exposing the modified III-V surface layer to a plasma to thereby remove the modified III-V surface layer. The disclosed methods are suitable for a wide range of applications, including etching processes for trenches and holes, fabrication of HEMTs, fabrication of LEDs, and improved selectivity in etching processes.

Claims

1. A method of etching a III-V material on a substrate, comprising:

a) exposing the III-V material to a chlorine-containing plasma without biasing the substrate to form a modified III-V surface layer; and

b) applying a bias voltage to the substrate while exposing the modified III-V surface layer to an inert plasma to thereby remove the modified III-V surface layer.

2. The method of claim 1, further comprising repeating (a) and (b) one or more times.

3. The method of claim 1, wherein the bias voltage is at a level such that the removal is in a self-limiting regime.

4. The method of claim 1, wherein the chlorine-containing plasma is generated from a process gas including a boron-containing compound, wherein about 0.5% to 10% (volumetric) of the process gas is the boron-containing compound.

5. The method of claim 1, further comprising performing one or more additional cycles of (a) and (b), wherein the bias voltage is lowered during the one or more additional cycles.

6. The method of claim 1, wherein the III-V material is GaN. The method of claim 6, wherein GaN is removed without removing an underlayer.

9. The method of claim 1, wherein the bias voltage is between about 20 V and 120 V.

10. The method of claim 1, wherein the bias voltage is between about 50 V and 120 V.

11. The method of claim 1, wherein the bias voltage is between about 50 V and 100 V.

12. The method of claim 1, wherein the chlorine-containing plasma is generated from a mixture of a chlorine-containing gas and a boron-containing gas.

13. The method of claim 1, wherein the chlorine-containing plasma is generated from a mixture of a Cl₂ and BCl₃.

14. The method of claim 1, wherein the inert plasma in (b) is an argon-containing plasma.

15. The method of claim 1, wherein the bias voltage is at level such that the etch is selective to an underlying material.

8. The method of claim 7, wherein the underlayer is AlGaN.

16. An apparatus for processing semiconductor substrates, the apparatus comprising:

a process chamber comprising a substrate support;

a power supply connected to the substrate support;

a plasma generator; and

a controller having at least one processor and a memory,

wherein the at least one processor and the memory are communicatively connected with one another, and

the memory stores machine-readable instructions for;

(i) introducing a chlorine-containing gas to the plasma generator;

(ii) igniting a chlorine-containing plasma in the plasma generator;

(iii) exposing a substrate to the chlorine-containing plasma to modify a III-V layer on the substrate without biasing the substrate;

(iv) introducing an inert gas to the plasma generator;

(v) igniting an inert plasma in the plasma generator; and

(vi) using the power supply to apply a bias voltage to the substrate while exposing the substrate to the inert plasma to remove the modified layer.