NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20160358855A1
• Filed: 01/06/2016
• Published: 12/08/2016
• Est. Priority Date: 06/05/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: OH, Kwang-Seok
• Granted Patent: US 9,570,393 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.

Claims

1. A nonvolatile memory device comprising:

a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked;

an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure;

an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer;

a protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer; and

contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.

2. The nonvolatile memory device of claim 1, wherein the contact plugs are directly connected to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.

3. The nonvolatile memory device of claim 1, wherein the protective layer is formed on a sidewall of the etch stop layer.

4. The nonvolatile memory device of claim 1, wherein the first interlayer dielectric layers and a memory cells are alternately stacked.

5. The nonvolatile memory device of claim 1, wherein the protective layer includes a material having etching selectivity relative to the etch stop layer.

6. The nonvolatile memory device of claim 1, wherein the etch stop layer includes a material having etching selectivity relative to the first and second interlayer dielectric layers.

7. The nonvolatile memory device of claim 1, further comprising:

metal interconnections formed over the second interlayer dielectric layer to contact with the contact plugs, respectively.

8. The nonvolatile memory device of claim 1, wherein the memory cell includes a metal material.

9. The nonvolatile memory device of claim 1, wherein the memory cell includes a tungsten layer.

10. The nonvolatile memory device of claim 1, wherein the first and second interlayer dielectric layers include oxide.

11. The nonvolatile memory device of claim 1, wherein the first and second interlayer dielectric layers include a material having etching selectivity.

12. The nonvolatile memory device of claim 1, wherein the etch stop layer includes nitride.

13. A method for fabricating a nonvolatile memory device, comprising:

forming a stair-shaped structure over a substrate, in which a first interlayer dielectric layer and a sacrificial layer are repeatedly stacked;

forming an etch stop layer and a second interlayer dielectric layer over the stair-shaped structure;

etching the second interlayer dielectric layer and the etch stop layer to form a groove;

forming a protective layer on a sidewall of the groove;

etching the stair-shaped structure over a bottom portion of the groove to form a first contact hole through which the substrate is exposed;

replacing each sacrificial layer of the stair-shaped structure with a plurality of memory cells;

forming an isolation layer to be filled in the first contact hole;

etching the second interlayer dielectric layer to form second contact holes to be coupled to the plurality of memory cells;

etching the etch stop layer under the second contact holes to open the plurality of memory cells; and

filling a conductive material in the second contact holes to form contact plugs.

14. The method of claim 13, wherein the replacing of each sacrificial layer with the memory cells comprises:

removing the sacrificial layer; and

filling a conductive material in an area from which the sacrificial layer has been removed.

15. The method of claim 14, wherein the removing of the sacrificial layer is performed through a wet process.

16. The method of claim 14, wherein the removing of the sacrificial layer is performed under a condition that the sacrificial layer has etching selectivity relative to the first interlayer dielectric layer and the protective layer.

17. The method of claim 13, wherein the forming of the protective layer comprises:

forming an insulating material along an entire structure including the groove; and

etching the insulating material to remain on the sidewall of the groove.

18. The method of claim 13, wherein the protective layer includes a material having etching selectivity relative to the etch stop layer and the sacrificial layer.

19. The method of claim 13, wherein the etch stop layer includes a material having etching selectivity relative to the second interlayer dielectric layer and the memory cells.

20. The method of claim 13, further comprising, after the forming of the contact plugs:

forming metal interconnections over the second interlayer dielectric layer to contact with the contact plugs, respectively.

21. A method for fabricating a nonvolatile memory device, comprising:

alternately layering first interlayer dielectric layers and sacrificial layers over a substrate to form a stair-shaped structure;

forming an etch stop layer and a second interlayer dielectric layer over the stair-shaped structure;

etching the second interlayer dielectric layer and the etch stop layer to form a groove;

forming a protective layer on a sidewall of the groove;

etching a bottom portion of the groove to form a first contact hole exposing the substrate; and

using the protective layer to substantially maintain the etch stop layer, as the etch stop layer was prior to removal of each sacrificial layer, while replacing each sacrificial layer of the stair-shaped structure with a plurality of memory cells.

22. The method of claim 21, further comprising:

filling the first contact hole with an isolation layer;

etching the second interlayer dielectric layer and the etch stop layer to the plurality of memory cells to form second contact holes; and

forming contact plugs by filling a conductive material in the second contact holes.

23. The method of claim 21, wherein the replacing of each sacrificial layer with the memory cells comprises:

filling a conductive material in an area from which the sacrificial layer has been removed.

24. The method of claim 23, wherein the removing of the sacrificial layer is performed through a wet process.

25. The method of claim 23, wherein the removing of the sacrificial layer is performed under a condition that the sacrificial layer has etching selectivity relative to the first interlayer dielectric layer and the protective layer.