SEMICONDUCTOR PACKAGE USING FLIP-CHIP TECHNOLOGY

• US 20160358877A1
• Filed: 08/16/2016
• Published: 12/08/2016
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: CHEN, Nan-Cheng, CHOU, Che-Ya, HSU, Wen-Sung
• Granted Patent: US 10,991,669 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05562 On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/498 : Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/0376 : Flush conductors, i.e. flush with the surface of the printed circuit
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting; Recessed electrode of component
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.

Claims

1. A semiconductor package, comprising:

a semiconductor device bonded to a base through a first conductive structure, wherein the semiconductor device comprises;

a carrier substrate comprising a conductive trace, wherein a portion of the conductive trace is elongated;

a second conductive structure above the carrier substrate, wherein a portion of the second conductive structure is in contact with the portion of the conductive trace; and

a semiconductor body mounted above the conductive trace, wherein the semiconductor body is connected to the second conductive structure.

2. The semiconductor package as claimed in claim 1, further comprising a third conductive structure bonded to a surface of the base facing away from the carrier substrate.

3. The semiconductor package as claimed in claim 2, wherein a size of the first conductive structure is greater than that of the second conductive structure and less than that of the third conductive structure.

4. The semiconductor package as claimed in claim 1, wherein the semiconductor device further comprises a molding compound surrounding the semiconductor body and the second conductive structure.

5. The semiconductor package as claimed in claim 1, wherein the conductive trace carries a signal or ground across at least a portion of the carrier substrate.

6. The semiconductor package as claimed in claim 1, wherein a top surface of the conductive trace is above, below or aligned to a surface of the carrier substrate facing the semiconductor body.

7. The semiconductor package as claimed in claim 1, wherein the second conductive structure comprises a solder cap in contact with the portion of the conductive trace.

8. A semiconductor package, comprising:

a semiconductor device bonded to a base through a first conductive structure, wherein the semiconductor device comprises;

a carrier substrate comprising a first conductive trace;

a second conductive structure above the carrier substrate, wherein a portion of the second conductive structure is in contact with the first conductive trace; and

a semiconductor die mounted above the first conductive trace, wherein a pad of the semiconductor die is connected to the second conductive structure and is wider than the first conductive trace.

9. The semiconductor package as claimed in claim 8, wherein the carrier substrate is wider than the semiconductor die.

10. The semiconductor package as claimed in claim 8, wherein the base is wider than the carrier substrate.

11. The semiconductor package as claimed in claim 8, wherein the base comprises:

a second conductive trace connecting to the first conductive structure;

a third conductive trace connecting to a third conductive structure bonded to a surface of the base facing away from the carrier substrate; and

a conductive via sandwiched between the third conductive trace and the second conductive trace.

12. The semiconductor package as claimed in claim 8, wherein a top surface of the first conductive trace is above, below or aligned to a surface of the

13. The semiconductor package as claimed in claim 8, wherein a shape of the first conductive trace is different from that of the pad.

14. The semiconductor package as claimed in claim 8, wherein the second conductive structure comprises a copper layer and a solder cap, and the copper layer and/or the solder cap is wider than the first conductive trace.

15. A semiconductor package, comprising:

a semiconductor device bonded to a base through a first conductive structures,

wherein the semiconductor device comprises;

a carrier substrate comprising a conductive trace, wherein the conductive trace is elongated and carries a signal or ground across at least a portion of the carrier substrate;

second conductive structures above the carrier substrate, wherein one of the second conductive structures is in contact with the conductive trace; and

a semiconductor die mounted above the conductive trace, wherein the semiconductor die is connected to the second conductive structures.

16. The semiconductor package as claimed in claim 15, further comprising third conductive structures bonded to a bottom surface of the base which is farther from the conductive trace than a top surface of the base.

17. The semiconductor package as claimed in claim 16, wherein a pitch between the first conductive structures is greater than that between the second conductive structures and less than that between the third conductive structures.

18. The semiconductor package as claimed in claim 15, wherein the carrier substrate is wider than the semiconductor die and narrower than the base.

19. The semiconductor package as claimed in claim 15, wherein an active surface of the semiconductor die faces the conductive trace.

20. The semiconductor package as claimed in claim 15, wherein the semiconductor device further comprises a second semiconductor die, wherein the semiconductor die and the second semiconductor die are positioned side by side or are vertically stacked.

21. The semiconductor package as claimed in claim 20, wherein the second semiconductor die has an active surface facing away from the conductive trace.

22. The semiconductor package as claimed in claim 15, further comprising molding compound surrounding the second conductive structures and in contact with the conductive trace.

23. The semiconductor package as claimed in claim 15, further comprising a heat slug attached to the base through an adhesive layer.

24. The semiconductor package as claimed in claim 15, further comprising a thermal interface material between the heat slug and the semiconductor