SPLIT GATE SEMICONDUCTOR DEVICE WITH CURVED GATE OXIDE PROFILE

• US 20160359018A1
• Filed: 08/15/2016
• Published: 12/08/2016
• Est. Priority Date: 10/21/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Gao, Yang, Chen, Kuo-In, Terrill, Kyle, Shi, Sharon
• Granted Patent: US 9,893,168 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.

Claims

1. A method of fabricating a split gate in a semiconductor device, said method comprising:

forming a first dielectric region along the sidewalls of a trench-like cavity in said semiconductor device;

forming a first gate electrode region within said cavity;

forming a second dielectric region in said cavity;

etching back said second dielectric region to form a concave surface; and

forming a second gate electrode region within said cavity.

2. The method of claim 1 further comprising etching back said first dielectric region prior to forming said second dielectric region.

3. The method of claim 1 further comprising producing a gate oxide layer on said concave surface and along said sidewalls prior to forming said second gate electrode region.

4. The method of claim 1 further comprising producing a thermal oxide layer along said sidewalls prior to forming said first dielectric region.

5. The method of claim 1 further comprising forming source and drain regions.

6. The method of claim 1 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor (MOSFET) device.

7. A method of fabricating a split gate in a semiconductor device, said method comprising:

producing a thermal oxide layer along the bottom surface and sidewall surfaces of a trench;

forming a first dielectric region over the thermal oxide layer, wherein a first layer comprises said thermal oxide layer and said first dielectric region;

forming a first gate electrode region over said first dielectric region;

removing portions of said first layer so that the height of said first layer is less than the height of said first gate electrode region;

forming a second dielectric region in said trench by depositing a dielectric layer over said first layer and said first gate electrode region;

etching back said second dielectric region to form a concave surface that extends across the entire width of said trench and that meets the sidewalls of said trench; and

forming a second gate electrode region within said trench.

8. The method of claim 7 further comprising etching back said first dielectric region prior to said step of forming said second dielectric region in said trench.

9. The method of claim 7 further comprising producing a gate oxide layer on said concave surface and along said sidewalls prior to said step of forming said second gate electrode region within said trench.

10. The method of claim 7 further comprising producing a thermal oxide layer along said sidewalls prior to forming said first dielectric region.

11. The method of claim 7 further comprising forming source and drain regions.

12. The method of claim 7 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor (MOSFET) device.

13. The method of claim 7 wherein a same material is present throughout said second dielectric region.