SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

• US 20160359566A1
• Filed: 08/08/2016
• Published: 12/08/2016
• Est. Priority Date: 12/19/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chih, Yu-Der, Yu, Hung-Chang, Lin, Kai-Chun, Kuo, Ying-Hao
• Granted Patent: US 9,742,497 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02B 6/12002 Three-dimensional structures
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/1226 involving surface plasmon interaction
• CPC Class Codes: G02B 6/34 utilising prism or grating G02B6/293 takes precedence
• CPC Class Codes: G02F 1/0157 using electro-absorption effects, e.g. Franz-Keldysh [FK] effect or quantum confined stark effect [QCSE]
• CPC Class Codes: G02F 1/025 in an optical waveguide structure G02F1/017, G02F1/2257 take precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 31/112 characterised by field-effect operation, e.g. junction field-effect phototransistor
• CPC Class Codes: H01S 5/021 Silicon based substrates
• CPC Class Codes: H01S 5/026 Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers stabilisation of output H01S5/06
• CPC Class Codes: H01S 5/0261 Non-optical elements, e.g. laser driver components, heaters H01S5/0265 takes precedence
• CPC Class Codes: H01S 5/0265 Intensity modulators intra-cavity modulators H01S5/0625
• CPC Class Codes: H01S 5/0285 Coatings with a controllable reflectivity
• CPC Class Codes: H01S 5/183 having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
• CPC Class Codes: H01S 5/18302 comprising an integrated optical modulator
• CPC Class Codes: H01S 5/18361 Structure of the reflectors, e.g. hybrid mirrors
• CPC Class Codes: H01S 5/3027 : IV compounds
• CPC Class Codes: H04B 10/43 : using a single component as both light source and receiver, e.g. using a photoemitter as a photoreceiver

Abstract

A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques.

Claims

1. A semiconductor arrangement, comprising:

a three dimensional (3D) integrated circuit (IC) structure comprising;

a first layer comprising;

a first gate of a first transistor; and

an optical transmitter, wherein a first source/drain region of the first transistor is coupled to a first serializer and a second source/drain region of the first transistor is coupled to the optical transmitter, and wherein the first transistor is configured to selectively couple the optical transmitter to the first serializer.

2. The semiconductor arrangement of claim 1, wherein the first layer comprises an optical receiver.

3. The semiconductor arrangement of claim 2, wherein the first layer comprises a second gate of a second transistor, wherein a first source/drain region of the second transistor is coupled to a first deserializer and a second source/drain region of the second transistor is coupled to the optical receiver, the second transistor configured to selectively couple the optical receiver to the first deserializer.

4. The semiconductor arrangement of claim 1, wherein the first layer is a passivation layer overlying a second layer and wherein the first source/drain region of the first transistor and the second source/drain region of the first transistor are disposed within the second layer.

5. The semiconductor arrangement of claim 4, the 3D IC structure comprising:

a doped area disposed within the second layer, wherein the optical transmitter overlies the doped area.

6. The semiconductor arrangement of claim 5, wherein the doped area electrically couples the optical transmitter to a voltage source.

7. The semiconductor arrangement of claim 1, wherein the optical transmitter comprises:

a first mirror;

a second mirror; and

a gain region disposed between the first mirror and the second mirror, wherein the first mirror and the second mirror and the gain region are disposed within the first layer.

8. The semiconductor arrangement of claim 1, the 3D IC structure comprising:

a second layer underlying the first layer; and

a waveguide in contact with the optical transmitter, wherein the waveguide extends through a portion of the first layer and a portion of the second layer.

9. The semiconductor arrangement of claim 1, the 3D IC structure comprising:

a second layer underlying the first layer; and

a grating coupler extending through a portion of the first layer and a portion of the second layer.

10. The semiconductor arrangement of claim 1, wherein the optical transmitter comprises:

a first modulator layer having a first set of optical properties;

a second modulator layer overlying the first modulator layer and having a second set of optical properties different than the first set of optical properties; and

a third modulator layer overlying the second modulator layer and having the first set of optical properties.

11. The semiconductor arrangement of claim 10, wherein the first modulator layer, the second modulator layer, and the third modulator layer are disposed within the first layer.

12. The semiconductor arrangement of claim 1, wherein the optical transmitter comprises:

a first grating coupler;

a second grating coupler; and

a waveguide modulator disposed between the first grating coupler and the second grating coupler.

13. The semiconductor arrangement of claim 12, the 3D IC structure comprising:

a second layer underlying the first layer, wherein the first grating coupler, the second grating coupler, and the waveguide modulator extend through a portion of the first layer and a portion of the second layer.

14. A semiconductor arrangement, comprising:

a three dimensional (3D) integrated circuit (IC) structure comprising;

a first layer comprising;

a gate of a transistor; and

an optical receiver, wherein a first source/drain region of the transistor is coupled to a deserializer and a second source/drain region of the transistor is coupled to the optical receiver, the transistor configured to selectively couple the optical receiver to the deserializer.

15. The semiconductor arrangement of claim 14, the 3D IC structure comprising:

a doped area disposed within a second layer underlying the first layer, wherein the optical receiver overlies the doped area and wherein the doped area electrically couples the optical receiver to a voltage source.

16. The semiconductor arrangement of claim 14, the 3D IC structure comprising:

a second layer underlying the first layer;

a plasmonic waveguide in contact with the optical receiver; and

a grating coupler in contact with the plasmonic waveguide, wherein the plasmonic waveguide and the grating coupler extend through a portion of the first layer and a portion of the second layer.

17. The semiconductor arrangement of claim 14, the optical receiver comprising a photo-transistor.

18. The semiconductor arrangement of claim 17, the 3D IC structure comprising:

a second layer underlying the first layer, wherein the photo-transistor comprises a first transistor layer extending into the second layer and wherein a sidewall of the first transistor layer is in contact with the first layer.

19. A method of making a semiconductor arrangement, comprising:

forming a three dimensional (3D) integrated circuit (IC) structure comprising;

doping a first layer to define a first source/drain region, a second source/drain region, and a doped area;

forming a second layer over the first layer;

etching the first layer to form a first opening between the first source/drain region and the second source/drain region and a second opening overlying the doped area;

forming a gate within the first opening; and

forming an optical receiver within the second opening.

20. The method of claim 19, the forming the 3D IC structure comprising:

forming a first connect to couple the first source/drain region to a deserializer; and

forming a second connect to couple the second source/drain region to the optical receiver.