MEMORY HAVING A STATIC CACHE AND A DYNAMIC CACHE

• US 20160364337A1
• Filed: 06/10/2015
• Published: 12/15/2016
• Est. Priority Date: 06/10/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hale, Christopher S., Ratnam, Sampath K., Muchherla, Kishore K.
• Granted Patent: US 9,697,134 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Claims

1. An apparatus, comprising:

a memory, wherein the memory includes;

a first portion configured to operate as a static single level cell (SLC) cache; and

a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

2. The apparatus of claim 1, wherein the second portion of the memory is configured to operate as multilevel cell memory when less than the entire first portion of the memory has data stored therein.

3. The apparatus of claim 1, wherein:

the first portion of the memory includes a first plurality of blocks of memory cells; and

the second portion of the memory includes a second plurality of blocks of memory cells.

4. The apparatus of claim 1, wherein the first portion of the memory is configured to operate as the static SLC cache for an entire lifetime of the memory.

5. The apparatus of claim 1, wherein a size of the second portion of the memory corresponds to a quantity of memory cells used by the memory to program data stored in single level cells of the memory to multilevel cells of the memory.

6. A method of operating memory, comprising:

configuring a first portion of a memory to operate as a static single level cell (SLC) cache; and

configuring a second portion of the memory to;

operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein; and

operate as multilevel cell (MLC) memory when less than the entire first portion of the memory has data stored therein.

7. The method of claim 6, wherein the method includes configuring the second portion of the memory to operate as MLC memory upon a quantity of program operations performed on the second portion of the memory meeting or exceeding a particular threshold.

8. The method of claim 6, wherein the method includes configuring the second portion of the memory to operate as MLC memory upon a quantity of erase operations performed on the second portion of the memory meeting or exceeding a particular threshold.

9. The method of claim 6, wherein the method includes configuring the second portion of the memory to operate as MLC memory upon a quantity of blocks in the second portion of the memory having data stored therein meeting or exceeding a particular threshold.

10. The method of claim 6, wherein the method includes configuring the second portion of the memory to operate as MLC memory upon a quantity of blocks of memory cells used by the memory to program data stored in single level cells of the memory to multilevel cells of the memory being equal to or greater than a quantity of blocks of memory cells in the second portion of the memory.

11. The method of claim 6, wherein configuring the second portion of the memory to operate as MLC memory includes configuring the second portion of the memory to operate as triple level memory.

12. An apparatus, comprising:

a memory having a plurality of blocks of memory cells; and

circuitry configured to;

operate a first number of the plurality of blocks as a static single level cell (SLC) cache; and

operate a second number of the plurality of blocks as a dynamic SLC cache when all of the first number of the blocks have data stored therein.

13. The apparatus of claim 12, wherein the circuitry is configured to:

program data to the first number of the blocks upon determining that less than all of the first number of the blocks have data stored therein; and

program data to the second number of the blocks upon determining that all of the first number of the blocks have data stored therein.

14. The apparatus of claim 12, wherein the plurality of blocks are part of a single die of the memory.

15. The apparatus of claim 12, wherein the circuitry is configured to:

perform erase operations on the first number of the plurality of blocks in SLC mode; and

perform erase operations on the second number of the plurality of blocks in multilevel cell mode.

16. The apparatus of claim 12, wherein the memory cells of the first number of the plurality of blocks are multilevel cells configured to operate in SLC mode.

17. The apparatus of claim 12, wherein the memory cells of the first number of the plurality of blocks are single level cells.

18. A method of operating memory, comprising:

receiving a command to program data to a memory;

determining, upon receiving the command, whether an entire first portion of the memory has data stored therein, wherein the first portion of the memory is configured to operate as a static single level cell (SLC) cache;

programming the data received in the command to the first portion of the memory upon determining that the entire first portion of the memory does not have data stored therein; and

programming the data received in the command to a second portion of the memory upon determining that the entire first portion of the memory has data stored therein, wherein the second portion of the memory is configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

19. The method of claim 18, wherein the method includes:

determining, upon determining that the entire first portion of the memory has data stored therein, whether a quantity of program or erase operations performed on the second portion of the memory meets or exceeds a particular threshold; and

programming the data received in the command to the second portion of the memory upon determining that the quantity of program or erase operations performed on the second portion of the memory does not meet or exceed the particular threshold.

20. The method of claim 19, wherein the method includes, upon determining that the quantity of program or erase operations performed on the second portion of the memory meets or exceeds the particular threshold:

programming data stored in the first portion of the memory to a third portion of the memory, wherein the third portion of the memory is configured to operate as multilevel cell memory; and

programming the data received in the command to the first portion of the memory.

21. The method of claim 19, wherein the method includes, upon determining that the quantity of program or erase operations performed on the second portion of the memory meets or exceeds a particular threshold:

configuring the second portion of the memory to operate as multilevel cell memory;

programming data stored in the first portion of the memory to the second portion of the memory; and

programming the data received in the command to the first portion of the memory.

22. The method of claim 18, wherein the method includes:

determining, upon determining that the entire first portion of the memory has data stored therein, whether a quantity of blocks in the second portion of the memory having data stored therein meets or exceeds a particular threshold; and

programming the data received in the command to the second portion of the memory upon determining that the quantity of blocks in the second portion of the memory having data stored therein does not meet or exceed the particular threshold.

23. The method of claim 22, wherein the method includes, upon determining that the quantity of blocks in the second portion of the memory having data stored therein meets or exceeds the particular threshold:

programming data stored in the first portion of the memory to a third portion of the memory, wherein the third portion of the memory is configured to operate as multilevel cell memory; and

programming the data received in the command to the first portion of the memory.

24. The method of claim 22, wherein the method includes, upon determining that the quantity of blocks in the second portion of the memory having data stored therein meets or exceeds the particular threshold:

configuring the second portion of the memory to operate as multilevel cell memory;

programming data stored in the first portion of the memory to the second portion of the memory; and

programming the data received in the command to the first portion of the memory.

25. The method of claim 18, wherein the method includes receiving the command from a host.