SIMULATING ACCESS LINES

• US 20160365129A1
• Filed: 06/10/2016
• Published: 12/15/2016
• Est. Priority Date: 06/12/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Willcock, Jeremiah J.
• Granted Patent: US 9,704,541 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1036 using data shift registers
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. The method can include storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and third number of sense lines.

Claims

1. A method comprising:

receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines;

storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and the third number of sense lines; and

performing an operation on the first bit-vector and the second bit-vector.

2. The method of claim 1, wherein performing the operation comprises performing at least one of a number of AND operations, OR operations, SHIFT operations, INVERT operations, and XOR operations without a sense line address access.

3. The method of claim 1, wherein the at least one of number of AND, OR, SHIFT, INVERT, XOR operations are performed using sensing circuitries coupled to respective columns of complementary sense lines, and wherein each of the sensing circuitries includes a sense amplifier comprising a primary latch and a compute component comprises a secondary latch.

4. The method of claim 1, wherein the format corresponds to a logical organization of the first access line and the first number of sense lines.

5. The method of claim 4, wherein storing the first bit-vector in a number of memory cells coupled to the first access line and the second number of sense lines comprises modifying the format associated with logical storing of the first bit-vector and storing the first bit-vector in a number of physical memory cells coupled to the first access line and the second number of sense lines.

6. The method of claim 1, wherein performing the operation on the first bit-vector and the second bit-vector comprises performing, in parallel, logical operations between respective bits of the first bit-vector and the second bit-vector.

7. The method of claim 1, further comprising storing at least a portion of the first bit-vector in the number of memory cells that are coupled to the first access line and a first, third, fifth, and seventh ordered sense lines of the number of sense lines.

8. The method of claim 7, further comprising storing the second bit-vector in the number of memory cells coupled to the first access line and a second, fourth, sixth, and eighth ordered sense lines of the number of sense lines.

9. The method of claim 7, wherein the method includes storing the first bit-vector in memory cells that are each separated from another of the memory cells storing the first bit-vector by each of the memory cells storing the second bit-vector.

10. The method of claim 1, further comprising:

receiving a third bit-vector in a format associated with storing the third bit-vector in memory cells coupled to a third access line and the first number of sense lines; and

storing the third bit-vector in memory cells coupled to the second access line and the second number of sense lines.

11. The method of claim 1, further comprising:

receiving a fourth bit-vector in a format associated with storing the fourth bit-vector in memory cells coupled to a fourth access line and the first number of sense lines; and

storing the fourth bit-vector in memory cells coupled to the second access line and the third number of sense lines.

12. An apparatus comprising:

a first group of memory cells coupled to a first access line and a number of first sense lines in a memory array and configured to store a first bit-vector;

a second group of memory cells coupled to the first access line and a number of second sense lines in the memory array and configured to store a second bit-vector; and

a controller configured to operate the sensing circuitry to;

shift bits of the second bit-vector to be stored in sensing circuitry associated with each corresponding bit of the first bit-vector; and

perform an operation on the first bit-vector and the second bit-vector.

13. The apparatus of claim 12, wherein a bit width of the second bit-vector is less than a quantity of memory cells coupled to the first access line.

14. The apparatus of claim 12, wherein performing the operation comprises performing the operation on a first bit of the first bit-vector stored in a memory cell coupled to the first access line and a first of the number of first sense lines and a first bit of the second bit-vector shifted to be stored in a corresponding sensing circuitry coupled to the first of the number of first sense lines.

15. The apparatus of claim 14, wherein performing the operation comprises performing the operation on each bit of the first bit-vector stored in memory cells coupled to the number of first sense lines and on each corresponding bit of the second bit-vector stored in memory cells coupled to the number of second sense lines in parallel.

16. A method, comprising:

shifting a first bit-vector stored in a first group of memory cells coupled to a number of first sense lines and to an access line of a memory array;

performing an operation on;

the first bit-vector; and

a second bit-vector stored in a second group of memory cells coupled to a number of second sense lines and the access line of the memory array;

wherein the first bit-vector is shifted before performing the operation; and

wherein the operation is performed using sensing circuitry comprising transistors formed on pitch with the memory cells of the memory array.

17. The method of claim 16, wherein the first bit-vector is shifted from sensing circuitry coupled to the number of first sense lines.

18. The method of claim 17, wherein the first bit-vector is shifted to sensing circuitry coupled to the number of second sense lines.

19. The method of claim 16, wherein a quantity of the number of first sense lines is a power of two and the quantity of the number of second sense lines is a power of two.

20. The method of claim 16, wherein the first bit-vector is shifted a quantity of bit positions that is associated with a quantity of the number of first sense lines and a quantity of the number of second sense lines.

21. The method of claim 20, wherein the quantity of bit positions associated with each of the first bit-vector and the second bit-vector is equal to half the quantity of the number of first sense lines.

22. An apparatus comprising:

a first number of memory cells coupled to a number of first sense lines and to an access line, wherein the first number of memory cells are configured to store a first bit-vector;

a second number of memory cells coupled to a number of second sense lines and to the access line, wherein the second number of memory cells are configured to store a second bit-vector;

a controller configured to operate sensing circuitry to;

receive the first bit-vector;

shift the first bit-vector; and

perform a number of operations on corresponding bits of the first bit-vector and the second bit-vector in parallel.

23. The apparatus of claim 22, wherein the controller configured to operate the sensing circuitry to perform the number of operations comprises the controller configured to operate the sensing circuitry to perform the number of operations without transferring data via an input/output (I/O) line.

24. The apparatus of claim 22, wherein the controller is configured to operate sensing circuitry to shift the first bit-vector by shifting portions of the first bit-vector in parallel.

25. The apparatus of claim 22, wherein the controller is further configured to receive instructions to store a simulated bit from a simulated access line i in the sensing circuitry.

26. The apparatus of claim 25, wherein the controller is further configured to store a bit from the first bit-vector in the sensing circuitry coupled to access line └

i/2┘

to store the simulated bit from the simulated access line i.

27. The apparatus of claim 22, wherein the controller is further configured to shift each of the bits from the first bit-vector to sensing circuitry coupled to access line i mod 2 to shift the first bit-vector.

28. The apparatus of claim 22, wherein an array having c sense lines and r access lines simulates an array having c/2 sense lines and 2r access lines, wherein the c sense lines include the number of first sense lines and the number of second sense lines and wherein the r access lines include the number of access lines.

29. The apparatus of claim 22, wherein the controller is further configured to provide separate function control bits for different portions of the number of first sense lines and the number of second sense lines.

30. The apparatus of claim 29, wherein the controller activates the different portions of the number of first sense lines independently via the separate function control bits.