SIMULATING ACCESS LINES
First Claim
1. A method comprising:
- receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines;
storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and the third number of sense lines; and
performing an operation on the first bit-vector and the second bit-vector.
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Accused Products
Abstract
Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. The method can include storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and third number of sense lines.
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Citations
30 Claims
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1. A method comprising:
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receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines; storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and the third number of sense lines; and performing an operation on the first bit-vector and the second bit-vector. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus comprising:
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a first group of memory cells coupled to a first access line and a number of first sense lines in a memory array and configured to store a first bit-vector; a second group of memory cells coupled to the first access line and a number of second sense lines in the memory array and configured to store a second bit-vector; and a controller configured to operate the sensing circuitry to; shift bits of the second bit-vector to be stored in sensing circuitry associated with each corresponding bit of the first bit-vector; and perform an operation on the first bit-vector and the second bit-vector. - View Dependent Claims (13, 14, 15)
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16. A method, comprising:
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shifting a first bit-vector stored in a first group of memory cells coupled to a number of first sense lines and to an access line of a memory array; performing an operation on; the first bit-vector; and a second bit-vector stored in a second group of memory cells coupled to a number of second sense lines and the access line of the memory array; wherein the first bit-vector is shifted before performing the operation; and wherein the operation is performed using sensing circuitry comprising transistors formed on pitch with the memory cells of the memory array. - View Dependent Claims (17, 18, 19, 20, 21)
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22. An apparatus comprising:
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a first number of memory cells coupled to a number of first sense lines and to an access line, wherein the first number of memory cells are configured to store a first bit-vector; a second number of memory cells coupled to a number of second sense lines and to the access line, wherein the second number of memory cells are configured to store a second bit-vector; a controller configured to operate sensing circuitry to; receive the first bit-vector; shift the first bit-vector; and perform a number of operations on corresponding bits of the first bit-vector and the second bit-vector in parallel. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
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Specification