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ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs

  • US 20160365347A1
  • Filed: 06/12/2015
  • Published: 12/15/2016
  • Est. Priority Date: 06/12/2015
  • Status: Active Grant
First Claim
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1. A semiconductor structure comprising:

  • at least one first semiconductor fin located in a first device region of a substrate, at least one second semiconductor fin located in a second device region of the substrate, at least one third semiconductor fin located in a third device region of the substrate, and at least one fourth semiconductor fin located in a fourth device region of the substrate; and

    a gate stack straddling over a channel portion of each of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor, and the at least one fourth semiconductor fin, the gate stack comprising;

    a first gate stack portion straddling over the channel portion of the first semiconductor fin and comprising;

    a first portion of a gate dielectric that is present on sidewalls and a bottom surface of a gate cavity laterally surrounded by an interlevel dielectric (ILD) layer located in a first device region, wherein the gate cavity exposes the channel portion of each of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor fin, and the at least one fourth semiconductor fin,a gate dielectric cap present on the first portion of the gate dielectric,a first portion of a p-type work function metal present on the gate dielectric cap,a first portion of a barrier layer portion present on the first portion of the p-type work functional metal, anda first portion of an n-type work function metal present on the first portion of the barrier layer portion;

    a second gate stack portion straddling over the channel portion of the second semiconductor fin and comprising;

    a second portion of the gate dielectric located in the second device region,a second portion of the p-type work function metal present on the second portion of the gate dielectric,a second portion of the barrier layer portion present on the second portion of the p-type work functional metal,a second portion of the n-type work function metal present on the second portion of the barrier layer portion, anda first portion of a gate electrode present on the second portion of the n-type work function metal;

    a third gate stack portion straddling over the channel portion of the third semiconductor fin and comprising;

    a third portion of the gate dielectric located in the third device region,a third portion of the barrier layer portion present on the third portion of the gate dielectric,a third portion of the n-type work function metal present on the third portion of the barrier layer portion,a metal cap present on the third portion of the n-type work function metal, anda second portion of the gate electrode present on the metal cap; and

    a fourth gate stack portion straddling over the channel portion of the fourth semiconductor fin and comprising;

    a fourth portion of the gate dielectric located in the third device region,a fourth portion of the barrier layer portion present on the fourth portion of the gate dielectric,a fourth portion of the n-type work function metal present on the fourth portion of the barrier layer portion, anda third portion of the gate electrode present on the fourth portion of the n-type work function metal.

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