ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs

• US 20160365347A1
• Filed: 06/12/2015
• Published: 12/15/2016
• Est. Priority Date: 06/12/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bao, Ruqiang, Krishnan, Siddarth A., Kwon, Unoh, Wong, Keith Kwong Hon
• Granted Patent: US 9,553,092 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/435 Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

Claims

1. A semiconductor structure comprising:

at least one first semiconductor fin located in a first device region of a substrate, at least one second semiconductor fin located in a second device region of the substrate, at least one third semiconductor fin located in a third device region of the substrate, and at least one fourth semiconductor fin located in a fourth device region of the substrate; and

a gate stack straddling over a channel portion of each of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor, and the at least one fourth semiconductor fin, the gate stack comprising;

a first gate stack portion straddling over the channel portion of the first semiconductor fin and comprising;

a first portion of a gate dielectric that is present on sidewalls and a bottom surface of a gate cavity laterally surrounded by an interlevel dielectric (ILD) layer located in a first device region, wherein the gate cavity exposes the channel portion of each of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor fin, and the at least one fourth semiconductor fin,

a gate dielectric cap present on the first portion of the gate dielectric,

a first portion of a p-type work function metal present on the gate dielectric cap,

a first portion of a barrier layer portion present on the first portion of the p-type work functional metal, and

a first portion of an n-type work function metal present on the first portion of the barrier layer portion;

a second gate stack portion straddling over the channel portion of the second semiconductor fin and comprising;

a second portion of the gate dielectric located in the second device region,

a second portion of the p-type work function metal present on the second portion of the gate dielectric,

a second portion of the barrier layer portion present on the second portion of the p-type work functional metal,

a second portion of the n-type work function metal present on the second portion of the barrier layer portion, and

a first portion of a gate electrode present on the second portion of the n-type work function metal;

a third gate stack portion straddling over the channel portion of the third semiconductor fin and comprising;

a third portion of the gate dielectric located in the third device region,

a third portion of the barrier layer portion present on the third portion of the gate dielectric,

a third portion of the n-type work function metal present on the third portion of the barrier layer portion,

a metal cap present on the third portion of the n-type work function metal, and

a second portion of the gate electrode present on the metal cap; and

a fourth gate stack portion straddling over the channel portion of the fourth semiconductor fin and comprising;

a fourth portion of the gate dielectric located in the third device region,

a fourth portion of the barrier layer portion present on the fourth portion of the gate dielectric,

a fourth portion of the n-type work function metal present on the fourth portion of the barrier layer portion, and

a third portion of the gate electrode present on the fourth portion of the n-type work function metal.

2. The semiconductor structure of claim 1, wherein the p-type work function metal comprises TiN.

3. The semiconductor structure of claim 1, wherein the n-type work function metal comprises TiAlC, TaAlC, TiAl, Ti, or Al.

4. The semiconductor structure of claim 1, wherein the barrier layer portion comprises TiN or TaN.

5. The semiconductor structure of claim 1, wherein the gate dielectric cap comprises TiN.

6. The semiconductor structure of claim 1, wherein the metal gap comprises TiN.

7. The semiconductor structure of claim 1, wherein the gate electrode comprises Al, Au, Ag, Co, Cu or W.

8. The semiconductor structure of claim 1, wherein the second gate stack portion further comprises a first portion of an etch stop layer portion present between the second portion of the n-type work function metal and the first portion of the gate electrode, the third gate stack portion further comprises a second portion of the etch stop layer portion present between the third portion of the n-type work function metal and the metal cap, and the fourth gate stack portion further comprises a third portion of the etch stop layer portion present between the forth portion of the n-type work function metal and the third portion of the gate electrode.

9. The semiconductor structure of claim 8, wherein the second gate stack portion further comprises a first portion of an adhesion layer portion present between the first portion of the etch stop layer portion and the first portion of the gate electrode, the third gate stack portion further comprises a second portion of the adhesion layer portion present between the metal cap and the second portion of the gate electrode, and the fourth gate stack portion further comprises a third portion of the adhesion layer portion present between the third portion of the etch stop layer portion and the third portion of the gate electrode.

10. The semiconductor structure of claim 9, wherein the etch stop layer portion comprises TiN, and the adhesion layer portion comprises Ti, TiN, or TiW.

11. The semiconductor structure of claim 1, wherein the first device region and the second device region are p-type fin field effect transistor regions, and wherein the third device region and the fourth device region are n-type fin field effect transistor regions.

19. The method of claim 11, further comprising removing portions of the gate electrode layer, the remaining portion of the metal cap layer, the n-type work function metal layer, the barrier layer, the remaining portion of the p-type work function metal layer, the remaining portion of the gate dielectric cap layer and the gate dielectric layer that are located above the topmost surface of the ILD layer.

20. The method of claim 11, wherein the forming the gate cavity comprises:

forming a sacrificial gate stack over the channel portion of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor fin, and the at least one fourth semiconductor fin;

forming a gate spacer on each sidewall of the sacrificial gate stack;

forming the ILD layer laterally surrounding the gate spacer; and

removing the sacrificial gate stack.

12. A method of forming a semiconductor structure comprising:

forming at least one first semiconductor fin located in a first device region of a substrate, at least one second semiconductor fin located in a second device region of the substrate, at least one third semiconductor fin located in a third device region of the substrate, and at least one fourth semiconductor fin located in a fourth device region of the substrate;

forming a gate cavity exposing a channel portion of each of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor fin, and the at least one fourth semiconductor fin, wherein the gate cavity is laterally surrounded by an interlevel dielectric (ILD) layer;

forming a gate dielectric layer on sidewalls and bottom surfaces of the gate cavity and a topmost surface of the ILD layer;

forming a gate dielectric cap layer over the gate dielectric layer;

removing a portion of the gate dielectric cap layer from the second, the third and the fourth device regions;

forming a p-type work function metal layer over a portion of the gate dielectric layer exposed in the second, the third and the fourth device regions and a remaining portion of the gate dielectric cap layer located in the first device region;

removing a portion of the p-type work function metal layer from the third and fourth device regions;

forming a barrier layer over a portion of the gate dielectric layer exposed in the third and the fourth device regions and a remaining portion of the p-type work function metal layer located in the first and second device regions;

forming an n-type work function metal layer over the barrier layer, wherein the n-type work function metal layer completely fills a first portion of the gate cavity located in the first device region;

forming a metal cap layer over the n-type work function metal layer;

removing a portion of the metal cap layer from the first, the second and the fourth device regions; and

forming a gate electrode layer over portions of the n-type work function metal layer exposed in the first, the second and the fourth device regions and a remaining portion of the metal cap layer located in the third device region, wherein the gate electrode layer completely fills a remaining portion of the gate cavity.

13. The method of claim 12, further comprising annealing the gate dielectric cap layer prior to the patterning the gate dielectric cap layer.

14. The method of claim 13, wherein the annealing the gate dielectric cap layer comprises:

forming a sacrificial cap layer on the gate dielectric cap layer;

annealing the gate dielectric cap layer at an elevated temperature; and

removing the sacrificial cap layer.

15. The method of claim 14, wherein the sacrificial cap layer comprises amorphous silicon or polysilicon.

16. The method of claim 14, further comprising forming a sacrificial hardmask layer on the annealed gate dielectric cap layer.

17. The method of claim 16, further comprising forming an etch stop layer on the n-type work function metal layer prior to the forming the metal cap layer.

18. The method of claim 17, further comprising forming an adhesion layer over the portions of the n-type work function metal layer exposed in the first, the second and the fourth device regions and the remaining portion of the metal cap layer located in the third device region prior to the forming the gate electrode layer.