METHOD FOR FORMING A SPLIT-GATE FLASH MEMORY CELL DEVICE WITH A LOW POWER LOGIC DEVICE
First Claim
1. A method for manufacturing an embedded flash memory device, the method comprising:
- forming a pair of gate stacks spaced over a semiconductor substrate, wherein the gate stacks include floating gates and control gates arranged over the floating gates;
forming a polysilicon layer over the gate stacks and the semiconductor substrate;
performing an etch back of regions of the polysilicon layer lining the gate stacks to below top surfaces of the gate stacks, while peripheral regions of the polysilicon layer are masked, to form an erase gate between the gate stacks;
forming hard masks over the erase gate, word line regions of the remaining polysilicon layer, and logic gate regions of the remaining polysilicon layer;
performing an etch through regions of the remaining polysilicon layer unmasked by the hard masks to form word lines and logic gates; and
forming an interlayer dielectric (ILD) layer, and contacts through the ILD layer, over the gate stacks, the erase gate, the word lines, and the logic gates.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.
-
Citations
20 Claims
-
1. A method for manufacturing an embedded flash memory device, the method comprising:
-
forming a pair of gate stacks spaced over a semiconductor substrate, wherein the gate stacks include floating gates and control gates arranged over the floating gates; forming a polysilicon layer over the gate stacks and the semiconductor substrate; performing an etch back of regions of the polysilicon layer lining the gate stacks to below top surfaces of the gate stacks, while peripheral regions of the polysilicon layer are masked, to form an erase gate between the gate stacks; forming hard masks over the erase gate, word line regions of the remaining polysilicon layer, and logic gate regions of the remaining polysilicon layer; performing an etch through regions of the remaining polysilicon layer unmasked by the hard masks to form word lines and logic gates; and forming an interlayer dielectric (ILD) layer, and contacts through the ILD layer, over the gate stacks, the erase gate, the word lines, and the logic gates. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method for manufacturing an embedded flash memory device, the method comprising:
-
forming a gate stack over a semiconductor substrate, wherein the gate stack includes a floating gate and a control gate arranged over the floating gate; forming a gate layer over the gate stacks and the semiconductor substrate, and further lining sidewalls of the gate stacks; forming an erase gate from the gate layer, wherein the erase gate is formed adjacent to a first side of the gate stack; and concurrently forming a word line and a logic gate from the gate layer, wherein the word line is formed adjacent to a second side of the gate stack, opposite the first side. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
-
-
19. A method for manufacturing an embedded flash memory device, the method comprising:
-
forming a pair of gate stacks spaced over a semiconductor substrate, wherein the gate stacks include floating gates and control gates arranged over the floating gates; forming a common gate layer over the gate stacks and the semiconductor substrate, and further lining sidewalls of the gate stacks; performing a first etch into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to further form an erase gate between the gate stacks; forming hard masks respectively over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer; and performing a second etch into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate respectively from the word line and logic gate regions of the common gate layer. - View Dependent Claims (20)
-
Specification