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PASSIVE DEVICES FOR INTEGRATION WITH THREE-DIMENSIONAL MEMORY DEVICES

  • US 20160365351A1
  • Filed: 06/15/2015
  • Published: 12/15/2016
  • Est. Priority Date: 06/15/2015
  • Status: Active Grant
First Claim
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1. A three dimensional memory device, comprising:

  • a memory device region containing a plurality of non-volatile memory devices;

    a peripheral device region containing active driver circuit devices;

    a first stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices;

    a stack of alternating layers including electrically insulating layers and electrically conductive layers located over a substrate, wherein the first stepped surface region contains first portions of the electrically insulating layers and first portions of the electrically conductive layers, and the first stepped region is located on a first side of the stack;

    a second stepped surface region containing second portions of the electrically insulating layers and second portions of the electrically conductive layers located on a second side of the stack;

    a plurality of semiconductor channels located in the memory device region in the stack, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

    a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels;

    a plurality of passive device contact via structures extending substantially perpendicular to the top surface of the substrate to the respective first portions of the electrically conductive layers in the first stepped surface region; and

    a plurality of control gate contact via structures extending substantially perpendicular to the top surface of the substrate to the respective second portions of the electrically conductive layers in the second stepped surface region.

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