PASSIVE DEVICES FOR INTEGRATION WITH THREE-DIMENSIONAL MEMORY DEVICES

• US 20160365351A1
• Filed: 06/15/2015
• Published: 12/15/2016
• Est. Priority Date: 06/15/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: MIWA, Toru, MATSUMOTO, Masahide, MIZUTANI, Yuki, KOKETSU, Hiroaki, NISHIKAWA, Masatoshi, HONMA, Ryoichi
• Granted Patent: US 9,646,981 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.

Claims

1. A three dimensional memory device, comprising:

a memory device region containing a plurality of non-volatile memory devices;

a peripheral device region containing active driver circuit devices;

a first stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices;

a stack of alternating layers including electrically insulating layers and electrically conductive layers located over a substrate, wherein the first stepped surface region contains first portions of the electrically insulating layers and first portions of the electrically conductive layers, and the first stepped region is located on a first side of the stack;

a second stepped surface region containing second portions of the electrically insulating layers and second portions of the electrically conductive layers located on a second side of the stack;

a plurality of semiconductor channels located in the memory device region in the stack, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels;

a plurality of passive device contact via structures extending substantially perpendicular to the top surface of the substrate to the respective first portions of the electrically conductive layers in the first stepped surface region; and

a plurality of control gate contact via structures extending substantially perpendicular to the top surface of the substrate to the respective second portions of the electrically conductive layers in the second stepped surface region.

3. The device of claim 1, wherein:

the peripheral device region contains sense amplifiers;

the second stepped surface region comprises a word line stepped surface region; and

the second portions of the electrically conductive layers comprise a plurality of control gate electrodes extending substantially parallel to the top surface of the substrate, and the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

4. The device of claim 3, wherein:

the plurality of passive driver circuit devices comprise a plurality of capacitors;

the first portions of the electrically conductive layers comprise a plurality of capacitor electrodes;

the first portions of the electrically insulating layers comprise capacitor dielectrics located between the capacitor electrodes; and

the respective first and the second portions of each of the electrically conductive layer are located at the same level above the substrate and are electrically insulated from each other.

5. The device of claim 3, wherein the plurality of passive driver circuit devices comprises a plurality of resistors.

2. (canceled)

6-15. -15. (canceled)

16. A method of forming a memory device comprising:

forming a plurality of memory devices in a memory device region;

forming a plurality of passive devices outside the memory device region;

forming a conductive layer in one deposition step such that a first portion of the conductive layer comprises a portion of at least one of the passive device and a second portion of the conductive layer forms a portion of at least one memory device;

forming a stack comprising an alternating plurality of electrically insulating layers and second material layers over a substrate;

forming trenches extending through the stack of alternating layers, wherein sidewalls of a patterned portion of the stack of alternating layers are physically exposed;

forming a patterned stack comprising an alternating plurality of the electrically insulating layers and electrically conductive layers, wherein the electrically conductive layers in the patterned stack are formed at each level of the second material layers, and the patterned stack is laterally contacted by a set of dielectric fill material portions formed within trenches; and

forming a plurality of contact via structures on the electrically conductive layers,

wherein;

portions of the electrically conductive layers located in a first stepped surface region between a peripheral device region and a memory device region constitute at least a portion of passive devices; and

forming the conductive layer comprises forming at least one of the electrically conductive layers or at least one of the plurality of contact via structures.

18. The method of claim 16, wherein:

the passive devices comprise capacitors;

a subset of the electrically insulating layers located in the first stepped surface region constitutes node dielectrics of the set of capacitors; and

each capacitor in the set comprises;

a first node that includes an underlying electrically conductive layer of a respective vertically neighboring pair and a respective contact via structure that extends upward from the underlying electrically conductive layer and through the dielectric material portion; and

a second node that includes an overlying electrically conductive layer of the respective vertically neighboring pair and a respective contact via structure that extends upward from the overlying electrically conductive layer and through the dielectric material portion.

19. The method of claim 18, further comprising replacing the second material layers with conductive material portions;

wherein;

the electrically conductive layers in the patterned stack comprises remaining portions of the conductive material portions;

the set of dielectric fill material portions is formed within the trenches after replacement of the second material layers with the conductive material portions; and

the second material layers are replaced with the conductive material portions by;

forming lateral recesses by etching the second material layers by introducing an etchant through one or more of the trenches;

depositing the conductive material portions within the lateral recesses; and

filling the one or more of the trenches with one or more dielectric fill material portions within the set of dielectric fill material portions.

20. The method of claim 18, further comprising:

filling each of the trenches with a dielectric material of a respective dielectric fill material portion;

forming a stepped surface region in which each underlying second material layer laterally extends farther than any overlying second material layer thereof; and

forming a dielectric material portion over the stepped surface region.

21. The method of claim 20, further comprising:

forming a support pillar trench through the alternating stack;

forming a dielectric pillar structure within the support pillar trench by depositing a first dielectric fill material;

forming lateral separation trenches through the alternating stack; and

forming dielectric trench fill structures by depositing a second dielectric fill material, wherein;

the set of dielectric fill material portions comprise the dielectric pillar structure and the dielectric trench fill structures;

the support pillar trench laterally extends along a same lateral direction as stepped surfaces within the stepped surface region; and

the lateral separation trenches laterally extend along a lateral direction that is perpendicular to the stepped surfaces within the stepped surface region.

22. The method of claim 20, wherein the dielectric material portion is a retro-stepped dielectric material portion in which a horizontal cross-sectional area of the dielectric material portion at a horizontal plane is not less than a horizontal cross-sectional area of the dielectric material portion at any horizontal plane that is more proximal to the substrate.

23. The method of claim 18, wherein:

each capacitor within the set of capacitors comprises two pairs of vertically neighboring electrically conductive layers;

the first node of the capacitor includes an underlying electrically conductive layer of a first vertically neighboring pair and an electrically conductive layer of a second vertically neighboring pair; and

the second node of the capacitor includes an overlying electrically conductive layer of the vertically neighboring pair and another electrically conductive layer of the second vertically neighboring pair.

24. The method of claim 16, wherein the passive devices comprise resistors.

17. (canceled)

25. (canceled)

26. A method of forming a memory device comprising:

forming a plurality of memory devices in a memory device region;

forming a plurality of passive devices outside the memory device region; and

forming a conductive layer in one deposition step such that a first portion of the conductive layer comprises a portion of at least one of the passive device and a second portion of the conductive layer forms a portion of at least one memory device;

wherein;

forming the plurality of memory devices in a memory device region comprises forming a monolithic three-dimensional memory device located over the substrate;

the monolithic three-dimensional memory device comprises;

a memory opening extending through the stack;

a memory film formed within the memory opening; and

a semiconductor channel formed within the memory film;

the passive devices are components of a peripheral device of the monolithic three-dimensional memory device;

the monolithic three-dimensional memory device is a vertical NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND memory device;

the substrate comprises a silicon substrate;

the vertical NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the three-dimensional array of NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the silicon substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the silicon substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

27. A method of forming a memory device comprising:

forming a plurality of memory devices in a memory device region;

forming a plurality of passive devices outside the memory device region; and

forming a conductive layer in one deposition step such that a first portion of the conductive layer comprises a portion of at least one of the passive device and a second portion of the conductive layer forms a portion of at least one memory device;

wherein;

forming the plurality of memory devices in a memory device region comprises forming a monolithic three-dimensional memory device located over the substrate;

the monolithic three-dimensional memory device comprises;

a memory opening extending through the stack;

a memory film formed within the memory opening; and

a semiconductor channel formed within the memory film; and

the first stepped surface region contains first portions of the electrically insulating layers and first portions of the electrically conductive layers, and the first stepped region is located on a first side of the stack.

28. The method of claim 27, further comprising forming a second stepped surface region containing second portions of the electrically insulating layers and second portions of the electrically conductive layers located on a second side of the stack during at the same time as forming the first stepped surface region.

29. The method of claim 28, wherein:

forming the plurality of contact via structures comprises forming a plurality of passive device contact via structures extending substantially perpendicular to the top surface of the substrate to the respective first portions of the electrically conductive layers in the first stepped surface region, and at the same time forming a plurality of control gate contact via structures extending substantially perpendicular to the top surface of the substrate to the respective second portions of the electrically conductive layers in the second stepped surface region;

the peripheral device region contains sense amplifiers;

the second stepped surface region comprises a word line stepped surface region; and

the second portions of the electrically conductive layers comprise a plurality of control gate electrodes extending substantially parallel to the top surface of the substrate, and the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.