PASSIVE DEVICES FOR INTEGRATION WITH THREE-DIMENSIONAL MEMORY DEVICES
First Claim
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1. A three dimensional memory device, comprising:
- a memory device region containing a plurality of non-volatile memory devices;
a peripheral device region containing active driver circuit devices;
a first stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices;
a stack of alternating layers including electrically insulating layers and electrically conductive layers located over a substrate, wherein the first stepped surface region contains first portions of the electrically insulating layers and first portions of the electrically conductive layers, and the first stepped region is located on a first side of the stack;
a second stepped surface region containing second portions of the electrically insulating layers and second portions of the electrically conductive layers located on a second side of the stack;
a plurality of semiconductor channels located in the memory device region in the stack, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels;
a plurality of passive device contact via structures extending substantially perpendicular to the top surface of the substrate to the respective first portions of the electrically conductive layers in the first stepped surface region; and
a plurality of control gate contact via structures extending substantially perpendicular to the top surface of the substrate to the respective second portions of the electrically conductive layers in the second stepped surface region.
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Abstract
A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.
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Citations
29 Claims
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1. A three dimensional memory device, comprising:
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a memory device region containing a plurality of non-volatile memory devices; a peripheral device region containing active driver circuit devices; a first stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices; a stack of alternating layers including electrically insulating layers and electrically conductive layers located over a substrate, wherein the first stepped surface region contains first portions of the electrically insulating layers and first portions of the electrically conductive layers, and the first stepped region is located on a first side of the stack; a second stepped surface region containing second portions of the electrically insulating layers and second portions of the electrically conductive layers located on a second side of the stack; a plurality of semiconductor channels located in the memory device region in the stack, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate; a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; a plurality of passive device contact via structures extending substantially perpendicular to the top surface of the substrate to the respective first portions of the electrically conductive layers in the first stepped surface region; and a plurality of control gate contact via structures extending substantially perpendicular to the top surface of the substrate to the respective second portions of the electrically conductive layers in the second stepped surface region. - View Dependent Claims (3, 4, 5)
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2. (canceled)
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6-15. -15. (canceled)
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16. A method of forming a memory device comprising:
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forming a plurality of memory devices in a memory device region; forming a plurality of passive devices outside the memory device region; forming a conductive layer in one deposition step such that a first portion of the conductive layer comprises a portion of at least one of the passive device and a second portion of the conductive layer forms a portion of at least one memory device; forming a stack comprising an alternating plurality of electrically insulating layers and second material layers over a substrate; forming trenches extending through the stack of alternating layers, wherein sidewalls of a patterned portion of the stack of alternating layers are physically exposed; forming a patterned stack comprising an alternating plurality of the electrically insulating layers and electrically conductive layers, wherein the electrically conductive layers in the patterned stack are formed at each level of the second material layers, and the patterned stack is laterally contacted by a set of dielectric fill material portions formed within trenches; and forming a plurality of contact via structures on the electrically conductive layers, wherein; portions of the electrically conductive layers located in a first stepped surface region between a peripheral device region and a memory device region constitute at least a portion of passive devices; and forming the conductive layer comprises forming at least one of the electrically conductive layers or at least one of the plurality of contact via structures. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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17. (canceled)
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25. (canceled)
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26. A method of forming a memory device comprising:
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forming a plurality of memory devices in a memory device region; forming a plurality of passive devices outside the memory device region; and forming a conductive layer in one deposition step such that a first portion of the conductive layer comprises a portion of at least one of the passive device and a second portion of the conductive layer forms a portion of at least one memory device; wherein; forming the plurality of memory devices in a memory device region comprises forming a monolithic three-dimensional memory device located over the substrate; the monolithic three-dimensional memory device comprises; a memory opening extending through the stack; a memory film formed within the memory opening; and a semiconductor channel formed within the memory film; the passive devices are components of a peripheral device of the monolithic three-dimensional memory device; the monolithic three-dimensional memory device is a vertical NAND memory device; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND memory device; the substrate comprises a silicon substrate; the vertical NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate; at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and the three-dimensional array of NAND strings comprises; a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the silicon substrate; a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the silicon substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.
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27. A method of forming a memory device comprising:
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forming a plurality of memory devices in a memory device region; forming a plurality of passive devices outside the memory device region; and forming a conductive layer in one deposition step such that a first portion of the conductive layer comprises a portion of at least one of the passive device and a second portion of the conductive layer forms a portion of at least one memory device; wherein; forming the plurality of memory devices in a memory device region comprises forming a monolithic three-dimensional memory device located over the substrate; the monolithic three-dimensional memory device comprises; a memory opening extending through the stack; a memory film formed within the memory opening; and a semiconductor channel formed within the memory film; and the first stepped surface region contains first portions of the electrically insulating layers and first portions of the electrically conductive layers, and the first stepped region is located on a first side of the stack. - View Dependent Claims (28, 29)
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Specification