SERIES RESISTANCE REDUCTION IN VERTICALLY STACKED SILICON NANOWIRE TRANSISTORS

• US 20160365411A1
• Filed: 06/15/2015
• Published: 12/15/2016
• Est. Priority Date: 06/15/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Yeh, Chun-Chen, Cai, Xiuyu, Liu, Qing, Xie, Ruilong
• Granted Patent: US 10,134,840 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

Claims

1. A method of fabricating a portion of a nanowire field effect transistor (FET), the method comprising:

forming a sacrificial layer and a nanowire layer;

removing a sidewall portion of the sacrificial layer;

forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer;

forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region; and

removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

2. The method of claim 1, wherein the sacrificial layer removal process comprises a wet process.

3. The method of claim 2, wherein a selectivity of the wet process to the diffusion block is below a predetermined threshold.

4. The method of claim 2, wherein the wet process comprises an etch.

5. The method of claim 4, wherein the etch comprises a reactive ion etch.

6. The method of claim 5, wherein the reactive ion etch causes an etch rate of the diffusion block that is below a predetermined threshold.

7. The method of claim 1, wherein the forming of the sacrificial layer and the nanowire layer comprises forming a stack comprising alternating sacrificial layers and nanowire layers.

8. The method of claim 1 further comprising:

forming a gate region around the nanowire layer;

wherein the gate region controls a flow of current from the source region through the nanowire layer into the drain region.

9. The method of claim 1 further comprising implanting dopant to the source region and the drain region to form at least one junction.

10. The method of claim 9, wherein the at least one junction comprises an extension junction of the nanowire layer.

11. A nanowire field effect transistor (FET) comprising:

a sacrificial layer and a nanowire layer;

a diffusion block formed adjacent to the sacrificial layer; and

a source region and a drain region positioned such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region;

wherein the diffusion block prevents a sacrificial layer removal process performed during fabrication of the nanowire FET from also removing portions of at least one of the source region and the drain region.

12. The nanowire FET of claim 11, wherein the sacrificial layer removal process comprises a wet process.

13. The nanowire FET of claim 12, wherein a selectivity of the wet process to the diffusion block is below a predetermined threshold.

14. The nanowire FET of claim 12, wherein the wet process comprises an etch.

15. The nanowire FET of claim 14, wherein the etch comprises a reactive ion etch.

16. The nanowire FET of claim 15, wherein the reactive ion etch causes an etch rate of the diffusion block that is below a predetermined threshold.

17. The nanowire FET of claim 11, wherein the sacrificial layer and the nanowire layer comprises a stack comprising alternating sacrificial layers and nanowire layers.

18. The nanowire FET of claim 11 further comprising:

a gate region around the nanowire layer;

wherein the gate region controls a flow of current from the source region through the nanowire layer into the drain region.

19. The nanowire FET of claim 11, wherein the source region and the drain region include dopants that form at least one junction.

20. The nanowire FET of claim 19, wherein the at least one junction comprises an extension junction of the nanowire layer.