SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20160365460A1
• Filed: 08/25/2016
• Published: 12/15/2016
• Est. Priority Date: 08/07/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, SAKATA, Junichiro, SAKAKURA, Masayuki, OIKAWA, Yoshiaki, OKAZAKI, Kenichi, MARUYAMA, Hotaka, TSUBUKU, Masashi
• Granted Patent: US 9,837,442 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/133528 Polarisers
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 : employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/247 : Amorphous materials
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.

Claims

1. (canceled)

2. A semiconductor device comprising:

a driver circuit portion comprising a shift register having a plurality of n-channel transistors; and

a pixel portion comprising a capacitor,

wherein the plurality of n-channel transistors each comprise an oxide semiconductor layer containing indium, gallium, and zinc, and

wherein the oxide semiconductor layer is interposed between two gate electrodes.

3. The semiconductor device according to claim 2, wherein one electrode of the capacitor is a same material as one of the two gate electrodes.

4. The semiconductor device according to claim 2, wherein one of the two gate electrodes is a transparent conductive film.

5. The semiconductor device according to claim 2,

wherein the pixel portion further comprises a pixel electrode, and

wherein the pixel electrode is a same material as one of the two gate electrodes.

6. The semiconductor device according to claim 2, wherein the two gate electrodes are electrically connected to each other.

7. The semiconductor device according to claim 2, wherein the oxide semiconductor layer comprises a portion being in an oxygen-excess state.

8. The semiconductor device according to claim 2,

wherein the plurality of n-channel transistors further each comprise a source electrode and a drain electrode,

wherein the oxide semiconductor layer comprises:

a first region in contact with the source electrode;

a second region in contact with the drain electrode; and

a third region between the first region and the second region, and

wherein a carrier concentration of the third region is lower than a carrier concentration of the first region and the second region.

9. A semiconductor device comprising:

a driver circuit portion comprising a shift register having a plurality of n-channel transistors; and

a pixel portion comprising a capacitor,

wherein the plurality of n-channel transistors each comprise an oxide semiconductor layer containing indium, tin, and zinc, and

wherein the oxide semiconductor layer is interposed between two gate electrodes.

10. The semiconductor device according to claim 9, wherein one electrode of the capacitor is a same material as one of the two gate electrodes.

11. The semiconductor device according to claim 9,

wherein the pixel portion further comprises a pixel electrode, and

wherein the pixel electrode is a same material as one of the two gate electrodes.

12. The semiconductor device according to claim 9, wherein one of the two gate electrodes is a transparent conductive film.

13. The semiconductor device according to claim 9, wherein the two gate electrodes are electrically connected to each other.

14. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises a portion being in an oxygen-excess state.

15. The semiconductor device according to claim 9,

wherein the plurality of n-channel transistors further each comprise a source electrode and a drain electrode,

wherein the oxide semiconductor layer comprises:

a first region in contact with the source electrode;

a second region in contact with the drain electrode; and

a third region between the first region and the second region, and

wherein a carrier concentration of the third region is lower than a carrier concentration of the first region and the second region.