ELECTRONIC CIRCUIT AND METHOD FOR TRANSFERRING DATA BETWEEN CLOCK DOMAINS

• US 20160365969A1
• Filed: 06/12/2015
• Published: 12/15/2016
• Est. Priority Date: 06/12/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Ministeru, Iulian
• Granted Patent: US 10,090,965 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828
• CPC Class Codes: H04L 25/4908 using mBnB codes
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade

Abstract

According to one embodiment, an electronic circuit is described comprising a first clock domain configured to operate according to a first clock signal, a second clock domain configured to operate according to a second clock signal different from the first clock signal, an encoding circuit, in the first clock domain, configured to encode data to be transmitted from the first clock domain to the second clock domain into codewords and configured to supply the codewords to an interface between the first clock domain and the second clock domain and a reception circuit, in the second clock domain, configured to receive data words from the interface, to decode valid codewords and to discard invalid codewords.

Claims

1. An electronic circuit comprising

a first clock domain configured to operate according to a first clock signal;

a second clock domain configured to operate according to a second clock signal different from the first clock signal;

an encoding circuit, in the first clock domain, configured to encode data to be transmitted from the first clock domain to the second clock domain into codewords and configured to supply the codewords to an interface between the first clock domain and the second clock domain; and

a reception circuit, in the second clock domain, configured to receive data words from the interface, to decode valid codewords and to discard invalid codewords.

2. The electronic circuit of claim 1, wherein the codewords are codewords of a predetermined code.

3. The electronic circuit of claim 2, wherein every two codewords of the code have a Hamming distance of two between them.

4. The electronic circuit of claim 2, wherein each codeword differs by one bit from a predetermined value.

5. The electronic circuit of claim 4, wherein the encoding circuit is configured to receive the predetermined value and to generate the codewords based on the predetermined value.

6. The electronic circuit of claim 2, wherein the reception circuit is configured to check, for a received data word, whether the data word is a codeword of the code and to decode the data word if it is a codeword of the code and to discard it else.

7. The electronic circuit of claim 1, wherein the reception circuit is configured to store decoded data words in a data register in the second clock domain.

8. The electronic circuit of claim 6, wherein the reception circuit is configured, for every data word received from the interface, to overwrite a previously decoded data word with the decoded data word in the data register if the data word is a valid codeword and to maintain the previously decoded data word in the data register if the data word is an invalid codeword.

9. The electronic circuit of claim 1, wherein the data to be transmitted are a sequence of binary values, wherein each binary digit is given by a line of a multi-bit data bus connected to the encoding circuit.

10. The electronic circuit of claim 9, wherein the encoding circuit is configured to encode each binary value into a codeword.

11. The electronic circuit of claim 1, wherein the interface comprises a synchronizer configured to synchronize the codewords to the second clock signal.

12. The electronic circuit of claim 11, wherein the encoding circuit is configured to supply the bits of each codeword in parallel to the interface by means of a plurality of bit lines and wherein the synchronizer comprises a synchronization circuit for each bit line of the plurality of plurality of bit lines.

13. The electronic circuit of claim 12, wherein the synchronizer is a multi-stage synchronizer.

14. The electronic circuit of claim 1, wherein the encoding circuit is configured to supply the codewords to the interface by means of a code register connected to the interface.

15. A method for transferring data between clock domains comprising

operating a first clock domain according to a first clock signal;

operating a second clock domain according to a second clock signal different from the first clock signal;

encoding data to be transmitted from the first clock domain to the second clock domain into codewords;

supplying the codewords to an interface between the first clock domain and the second clock domain;

receiving data words in the second clock domain from the interface;

decoding valid codewords; and

discarding invalid codewords.