INFORMATION PROCESSING APPARATUS AND DATA ACCESSING METHOD

• US 20160370999A1
• Filed: 06/06/2016
• Published: 12/22/2016
• Est. Priority Date: 06/16/2015
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: KONNO, Hiroki
• Granted Patent: US 9,983,798 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

An information processing apparatus includes a first memory including a first portion and a second portion, the first portion including a plurality of regions, and a processor configured to read first data stored in a first region of the plurality of regions, move the first data stored in the first region to a second region, generate management data indicating that the first data is moved to the second region, store the management data in the second portion of the first memory, obtain information indicating a relation between the first data and location of the management data in the first memory, in response to a request to read the first data stored in the second region, access the management data based on the information, and read the first data stored in the second region.

Claims

1. An information processing apparatus comprising:

a first memory including a first portion and a second portion, the first portion including a plurality of regions; and

a processor coupled to the first memory and configured to;

read first data stored in a first region of the plurality of regions of the first memory,

move the first data stored in the first region to a second region of the plurality of regions,

generate management data indicating that the first data is moved to the second region of the plurality of regions,

store the management data in the second portion of the first memory,

obtain information indicating a relation between the first data and location of the management data in the first memory,

in response to a request to read the first data stored in the second region, access the management data based on the information, and

read the first data stored in the second region.

2. The information processing apparatus according to claim 1, wherein

the processor including a second memory, and

the processor is further configured to:

after read the first data stored in the first region of the plurality of regions of the first memory, store the first data in the second memory, and

delete, from the second memory, data earliest stored in the second memory, when a capacity of the second memory is insufficient for storing new data.

3. The information processing apparatus according to claim 2,

wherein the second memory includes a cache memory, and

the processor is further configured to, when the first data is stored in the cache memory, access the first data in the cache memory in response to the request to read the first data.

4. The information processing apparatus according to claim 1, wherein the processor is further configured to determine the second region for storing the first data based on an access frequency to the first data.

5. The information processing apparatus according to claim 1, wherein the processor is further configured to determine the second region every time a certain period of time has elapsed.

6. The information processing apparatus according to claim 1, wherein the processor is further configured to determine the second region, based on a number of times the first data is accessed.

7. The information processing apparatus according to claim 1, wherein

the information processing apparatus includes a base station, and

the processor is further configured to determine the second region, based on a load on the information processing apparatus for communications with a mobile station.

8. The information processing apparatus according to claim 7, wherein the processor is further configured to determine the second region, based on a priority determined for the first data, in response to a change over time in the load.

9. The information processing apparatus according to claim 5, wherein the processor is further configured to determine the second region, based on a priority determined for the first data, when the load in each of a plurality of times is within a certain range centered on a reference value that is determined for each of the plurality of times.

10. The information processing apparatus according to claim 3, wherein the processor is further configured to, when the first data stored in the first region is accessed, store, into the cache memory, second data stored in a third region next to the first region of the plurality of regions.

11. A data accessing method using a first memory and a processor coupled to the first memory, the first memory including a first portion and a second portion, the first portion including a plurality of regions, the data accessing method comprising:

reading first data stored in a first region of the plurality of regions of the first portion of the first memory;

moving the first data stored in the first region to a second region of the plurality of regions;

generating management data indicating that the first data is moved to the second region;

storing the management data in the second portion of the first memory;

obtaining information indicating a relation between the first data and location of the management data in the first memory;

in response to a request to read the first data stored in the second region, accessing the management data based on the information; and

reading the first data stored in the second region.

12. The data accessing method according to claim 11, further comprising:

after reading the first data stored in the first region of the plurality of regions of the first memory, storing the first data in a second memory included in the processor; and

deleting, from the second memory, data earliest stored in the second memory, when a capacity of the second memory is insufficient for storing new data.

13. The data accessing method according to claim 12, wherein

the second memory includes a cache memory, and

the data accessing method further comprises:

when the first data is stored in the cache memory, accessing the first data in the cache memory in response to the request to read the first data stored in the second region.

14. The data accessing method according to claim 11, further comprising:

determining the second region for storing the first data based on an access frequency to the first data.

15. The data accessing method according to claim 11, further comprising:

determining the second region every time a certain period of time has elapsed.

16. The data accessing method according to claim 11, further comprising:

determining the second region, based on a number of times the first data is accessed.

17. The data accessing method according to claim 11, wherein the first memory and the processor are included in a base station, and the data accessing method further comprises determining the second region, based on a load on the base station for communications with a mobile station.

18. The data accessing method according to claim 17, wherein the determining of the second region is executed based on a priority determined for the first data in response to a change over time in the load.

19. The data accessing method according to claim 15, wherein the determining of the second region is executed based on a priority determined for the first data, when a load in each of a plurality of times is within a certain range centered on a reference value that is determined for each of the plurality of times.

20. The data accessing method according to claim 13, further comprising:

when the first data stored in the first region is accessed, storing second data stored in a third region next to the first region of the plurality of regions into the cache memory.