MEMORY UNIT FOR AUTOMATICALLY MULTIPLYING THE CONTENT OF A MEMORY LOCATION, AND DATA NETWORK HAVING A MEMORY UNIT

• US 20160371010A1
• Filed: 05/17/2016
• Published: 12/22/2016
• Est. Priority Date: 06/19/2015
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Kramer, Simon, Saballus, Bjoern
• Granted Patent: US 10,162,560 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/173 Vehicle or other transportation
• CPC Class Codes: G06F 2212/206 Memory mapped I/O
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A memory unit, which has a plurality of memory locations for accommodating data and which is designed to copy the content of a first memory location of the memory unit, when this first memory location is written, automatically into a first memory location at least of one other memory unit, the first memory location of the at least one other memory unit being readable and writable independently of the first memory location of the memory unit; and to a data network having at least two such memory units, a transmitter and at least one receiver, the transmitter being designed to write a datum to be sent into the first memory location of a first of the at least two memory units, and the at least one receiver being designed to read and to process the datum from the first memory location of a second memory unit of the at least two memory units.

Claims

1. A memory unit, which has a plurality of memory locations for accommodating data, and which is designed to copy the content of a first memory location of the memory unit, when the first memory location of the memory unit is written, automatically into a first memory location of at least one other memory unit, the first memory location of the at least one other memory unit being able to be read and written independently of the first memory location of the memory unit.

2. The memory unit as recited in claim 1, wherein an address of the first memory location of the at least one other memory unit is stored in a second memory location of the plurality of memory locations.

3. The memory unit as recited in claim 1, wherein the memory unit is part of an integrated circuit.

4. A data network, comprising:

at least two memory units memory unit, each of which has a plurality of memory locations for accommodating data, and each of which is designed to copy the content of a first memory location of the respective memory unit, when the first memory location of the respective memory unit is written, automatically into a first memory location of at least one other memory unit, the first memory location of the at least one other memory unit being able to be read and written independently of the first memory location of the respective memory unit; and

a transmitter and at least one receiver, wherein the transmitter is designed to write a datum to be sent into the first memory location of a first of the at least two memory units, and wherein the at least one receiver is designed to read and process the datum from the first memory location of a second memory unit of the at least two memory units.

5. The data network as recited in claim 4, wherein the datum to be sent contains at least one of:

i) no address of the at least one receiver, and ii) no address of a memory location of the plurality of memory locations of the second memory unit of the at least two memory units.

6. The data network as recited in claim 4, wherein the second memory unit of the at least two memory units is designed to register with the first memory unit of the at least two memory units for receiving the data.

7. The data network as recited in claim 4, wherein the transmitter and the first memory unit are part of a first processing unit, and wherein the second memory unit and at least one receiver are part of a second processing unit (120).

8. The data network as recited in claim 4, which is developed as a multicore or many-core system.

9. The data network as recited in claim 4, which is developed as a control unit, wherein the transmitter and the receiver are software processes in the control unit.

10. The data network as recited in claim 4, further comprising multiple control units, wherein the transmitter and the receiver are software processes in different of the multiple control units.

11. The data network as recited in claim 4, wherein the data network is part of a motor vehicle data network.