APPARATUSES AND METHODS FOR DATA TRANSFER FROM SENSING CIRCUITRY TO A CONTROLLER

• US 20160371033A1
• Filed: 06/16/2016
• Published: 12/22/2016
• Est. Priority Date: 06/22/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Shawver, James J., La Fratta, Patrick A.
• Granted Patent: US 9,921,777 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.

Claims

1. An apparatus, comprising:

a controller coupled to a memory device, the controller configured to;

execute a command to transfer data from a latch component to a register file in the controller, wherein the memory device comprises;

an array of memory cells;

the latch component coupled to rows of the array via a plurality of columns of the memory cells, the latch component including a latch selectably coupled to each of the columns and configured to implement the command to transfer the data; and

a data line to couple the latch component to the register file to transfer the data; and

wherein the controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.

2. The apparatus of claim 1, wherein the apparatus further comprises:

fetch circuitry in the controller configured to direct a transfer of particular data from the array to;

a latch stripe configured to include a number of a plurality of latches of the latch component that corresponds to a number of link lines for the plurality of columns of the memory cells; and

wherein the number of the plurality of latches is selectably coupled to a corresponding plurality of the data lines.

3. The apparatus of claim 1, wherein:

a number of a plurality of latch stripes corresponds to a number of a plurality of banks in the memory device; and

a number of a plurality of controllers corresponds to the number of the plurality of banks in the memory device.

4. The apparatus of claim 1, wherein the apparatus further comprises:

multiplexer circuitry in the controller to selectably transfer data from a particular column of memory cells of the memory device by being selectably coupled to a plurality of latches in the latch component.

5. The apparatus of claim 1, wherein the apparatus further comprises:

a latch stripe including a number of latches configured to transfer an amount of data retrieved from a row of the memory device in parallel to a plurality of shared I/O lines; and

wherein the amount of data corresponds to at least a thousand bit width of a plurality of shared I/O lines.

6. The apparatus of claim 5, wherein a number of the plurality of shared I/O lines corresponds to a number of bits wide shared I/O line.

7. The apparatus of claim 1, wherein the apparatus further comprises:

a latch stripe configured to transfer data retrieved from a row of the memory device as a plurality of subsets when coupled to a plurality of shared I/O lines; and

wherein an amount of at least a first subset of the data corresponds to at least a thousand bit width of a plurality of shared I/O lines.

8. The apparatus of claim 1, wherein the controller is further configured to:

transfer the data from a selected row and selected latches in the latch component to the register file in the controller via a plurality of data lines.

9. The apparatus of claim 1, wherein the transferred data includes a register value used for execution of a received set of instructions to perform an operation.

10. An apparatus, comprising:

a memory device configured to connect to a host, wherein the memory device includes;

an array of memory cells; and

a controller having a register file selectably coupled to the array via sensing circuitry, the controller configured to;

receive a first set of instructions from the host to perform an operation; and

enable execution by the controller of the first set of instructions by retrieval of a second set of instructions from a component of the controller;

send the second set of instructions to direct the sensing circuitry to;

retrieve from the array a register value used for the execution of the first set of instructions; and

transfer the register value to the controller; and

store the register value in the register file of the controller.

11. The apparatus of claim 10, wherein the sensing circuitry is coupled to the array via:

a plurality of sense lines; and

a plurality of latch component links.

12. The apparatus of claim 10, wherein the sensing circuitry comprises:

a latch component configured to retrieve the register value from the array; and

sense amplifiers for other operations.

13. The apparatus of claim 10, wherein the apparatus further comprises:

a latch component that comprises;

a plurality of latches; and

wherein the plurality of latches each are configured with a store for retrieved data values, including the retrieved register value.

14. The apparatus of claim 10, wherein the apparatus further comprises:

a latch component that is on chip with the array and is coupled to the array via a plurality of sense lines.

15. The apparatus of claim 10, wherein the apparatus further comprises:

a latch component; and

wherein the latch component is configured to transfer data values retrieved from a row, including the register value, as a plurality of subsets when selectably coupled to a plurality of shared I/O lines.

16. The apparatus of claim 10, wherein the apparatus further comprises:

a multiplexer in the controller configured to determine data values, including the register value, stored by selected latches in a latch component to be input to a plurality of data lines.

17. The apparatus of claim 10, wherein the register file is configured to store the register value received as subsets of data values input to a plurality of shared I/O lines.

18. An apparatus, comprising:

a memory device configured to be coupled to a host, wherein the memory device comprises;

an array of memory cells; and

an operation manager with a register file, the operation manager located in a controller on chip with the array and selectably coupled to the array via a latch component, the operation manager configured to;

execute a first command from the controller to transfer a register value in a bank via the latch component to the register file associated with the operation manager;

issue a second command to fetch circuitry in the controller configured to direct a retrieval of the register value from the bank to a plurality of latches of the latch component;

transfer from the plurality of latches the register value, retrieved by the fetch circuitry, as data values input to a plurality of data lines; and

store the transferred register value in the register file to be provided for execution of a received set of instructions to perform an operation.

19. The apparatus of claim 18, wherein the apparatus further comprises:

a plurality of latches in the latch component configured to selectably transfer cached data sensed from a particular row of memory cells by being selectably coupled to a data line.

20. The apparatus of claim 19, wherein a number of shared I/O lines formed in the array is determined by division of a number of columns in the array by the respective plurality of latches in the latch component selectably coupled to the shared I/O line.

21. The apparatus of claim 18, wherein the apparatus further comprises:

a multiplexer in the controller to select a latch of the plurality of latches to couple to the shared I/O line.

22. The apparatus of claim 18, wherein:

the operation manager provides the stored register value for execution of a set of instructions received from a host; and

wherein the set of instructions is executed without an additional retrieval operation for the register value in the array.

23. The apparatus of claim 18, wherein the operation manager:

directs fetch circuitry in the controller to execute a fetch operation for the register value from a particular row of the array; and

the operation manager is selectably coupled to the latches for the transfer of the register value to the register file.

24. The apparatus of claim 18, wherein:

the array includes a column of memory cells having a pair of complementary sense lines; and

wherein the latch component comprises a latch selectably coupled to each of the pair of complementary sense lines.

25. The apparatus of claim 18, wherein:

each of the plurality of banks is separately configured with an operation manager located in a controller to execute a command to transfer register values in that bank from a latch component to a register file.

26. A method for operating a memory device to perform data transfer from sensing circuitry to a controller, comprising:

configuring latches and the controller of the memory device to couple via a plurality of data lines, wherein the memory device includes;

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a latch component, wherein the latch component includes a plurality of the latches; and

the controller selectably coupled to the array and the plurality of the latches via the plurality of data lines;

receiving a command from control logic of the controller to transfer a register value stored in the array to a register file in an operation manager of the controller; and

transferring the register value to the register file in the operation manager from the selectably coupled latches via the plurality of data lines.

27. The method of claim 26, wherein the method further comprises:

the operation manager initiating execution of stored instructions via data transfer control logic of the controller; and

the data transfer control logic selecting a first multiplexer of the controller coupled to the latches as a data path for input of the plurality of subsets from the first multiplexer to a second multiplexer of the controller coupled to the register file.

28. The method of claim 26, wherein the method further comprises:

executing stored instructions by;

selecting an address line to the register file;

selecting lines of a second multiplexer of the controller coupled to the register file as the data path for input of particular subsets from a first multiplexer of the controller coupled to the latches; and

sending a signal to enable transfer of the plurality of subsets to the register file via the second multiplexer.

29. The method of claim 26, wherein the method further comprises:

executing stored instructions by;

the operation manager directing that a fetch operation be performed via fetch circuitry of the controller; and

the fetch circuitry initiating the fetch operation for the register value in the array.

30. The method of claim 26, wherein the method further comprises:

executing stored instructions by;

performing a fetch operation via fetch circuitry of the controller for the register value in the array;

sending an idle signal to the control logic to idle a clock that controls progress through the stored instructions while the fetch circuitry performs the fetch operation; and

sending a signal to disable transfer of the plurality of subsets to the register file via a second multiplexer of the controller coupled to the register file while the fetch circuitry performs the fetch operation.

31. The method of claim 26, wherein the method further comprises:

executing stored instructions by;

after finding the register value, fetch circuitry of the controller directing that the register value be retrieved to the plurality of the latches;

the fetch circuitry sending a signal to enable transfer of the plurality of subsets to the register file via a second multiplexer of the controller; and

the fetch circuitry sending a signal to the control logic that reverses an idle signal that idles a clock to reinitiate progress through the stored instructions.

32. The method of claim 26, wherein the method further comprises:

executing stored instructions by;

sending a signal to enable transfer to a coupled register file, via a second multiplexer of the controller, of the plurality of subsets of the register value retrieved to the plurality of latches; and

sending a signal to the operation manager directing that a write operation be performed to store the plurality of subsets of the register value in the register file.

33. The method of claim 32, wherein the method further comprises:

after performing the write operation, executing the stored instructions by;

data transfer control logic of the controller decoupling a first multiplexer of the controller coupled to the latches and decoupling the second multiplexer coupled to the register file; and

disabling the signal to perform the write operation.

34. The method of claim 26, wherein the method further comprises:

executing stored instructions by;

selecting a first multiplexer in data transfer control logic of the controller, after the first multiplexer is decoupled from the latches, to enable the operation manager to store local data in the register file.

35. The method of claim 26, wherein the method further comprises:

executing stored instructions by;

interrupting a write operation to store the plurality of subsets in the register file; and

directing that a different subset of the data retrieved to the plurality of latches be transferred to the operation manager either for storage in the register file or for another use.