BUS-BIT-ORDER ASCERTAINMENT

• US 20160371211A1
• Filed: 07/23/2015
• Published: 12/22/2016
• Est. Priority Date: 06/16/2015
• Status: Abandoned Application

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Isachar, Ori, Semo, Gil, Kushtai, Guy, Lazmi, Tal
• Application Number:
  US14/806,795
• Publication Number:
  US 20160371211A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 13/4013 with data re-ordering, e.g. Endian conversion
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An apparatus for use with a memory device that has a plurality of memory-device terminals having respective unique bit significances is described. The apparatus includes a memory controller, which includes (i) a plurality of external terminals, each one of the external terminals configured to be in communication with a respective one of the memory-device terminals, (ii) a plurality of internal terminals having respective unique bit significances, (iii) a switching unit, and (iv) a processor. The processor is configured to drive the memory device to communicate a predetermined sequence of bit patterns to the controller, and, in response to the sequence of bit patterns, drive the switching unit to connect each one of the external terminals to a respective one of the internal terminals having the bit significance of the memory-device terminal with which the external terminal is in communication. Other embodiments are also described.

Claims

1. An apparatus for use with a memory device that has a plurality of memory-device terminals having respective unique bit significances, the apparatus comprising:

a memory controller, comprising;

a plurality of external terminals, each one of the external terminals configured to be in communication with a respective one of the memory-device terminals;

a plurality of internal terminals having respective unique bit significances;

a switching unit; and

a processor, configured to;

drive the memory device to communicate a predetermined sequence of bit patterns to the controller; and

in response to the sequence of bit patterns, drive the switching unit to connect each one of the external terminals to a respective one of the internal terminals having the bit significance of the memory-device terminal with which the external terminal is in communication.

2. The apparatus according to claim 1, wherein:

the switching unit comprises a plurality of multiplexers; and

the processor is configured to drive the switching unit to connect each one of the external terminals to the respective one of the internal terminals by controlling the multiplexers.

3. The apparatus according to claim 2, wherein each one of the multiplexers is connected to (i) a respective one of the external terminals, and (ii) at least two of the internal terminals.

4. The apparatus according to claim 2, wherein each one of the multiplexers is connected to (i) a respective one of the internal terminals, and (ii) at least two of the external terminals.

5. The apparatus according to claim 1, wherein the switching unit is configured to preserve connections between the internal terminals and the external terminals, following a powering-down of the controller.

6. The apparatus according to claim 1, wherein the sequence of bit patterns includes at least N−

1 bit patterns, N being a number of the external terminals, each of the at least N−

1 bit patterns including exactly one bit having a value selected from the group consisting of;

0, and 1,

the processor being configured to drive the memory device to communicate the sequence to the controller.

7. The apparatus according to claim 1, wherein the processor is configured to drive the memory device to communicate the predetermined sequence of bit patterns to the controller by communicating a reset command to the memory device.

8. The apparatus according to claim 1, wherein the processor is configured to:

communicate a reset command to the memory device; and

following the communication of the reset command and before beginning regular communication with the memory device, by communicating one or more driving signals to the memory device, drive the memory device to communicate the predetermined sequence of bit patterns to the controller.

9. The apparatus according to claim 8, wherein the processor is configured to, by communicating each one of the driving signals to the memory device, drive the memory device to communicate a respective one of the bit patterns to the controller.

10. The apparatus according to claim 8, wherein the processor is configured to drive the memory device to communicate the predetermined sequence of bit patterns to the controller by communicating exactly one driving signal to the memory device.

11. A method for facilitating communication between a memory controller and a memory device that has a plurality of memory-device terminals having respective unique bit significances, comprising:

driving, by a processor of the memory controller, the memory device to communicate a predetermined sequence of bit patterns to the controller; and

in response to the sequence of bit patterns, driving, by the processor, a switching unit to connect each external terminal of the memory controller to a respective one of internal terminals of the memory controller having the bit significance of the memory-device terminal with which the external terminal is in communication.

12. The method according to claim 11, wherein the switching unit includes a plurality of multiplexers, and wherein driving the switching unit to connect each one of the external terminals to the respective one of the internal terminals comprises driving the switching unit to connect each one of the external terminals to the respective one of the internal terminals by controlling the multiplexers.

13. The method according to claim 11, wherein driving the memory device to communicate the sequence comprises driving the memory device to communicate the sequence by communicating a reset command to the memory device.

14. The method according to claim 11, further comprising communicating a reset command to the memory device, wherein driving the memory device to communicate the sequence comprises, following the communication of the reset command and before beginning regular communication with the memory device, driving the memory device to communicate the sequence.

15. The method according to claim 11, wherein driving the memory device to communicate the predetermined sequence of bit patterns to the controller comprises communicating a plurality of driving signals to the memory device, each of the driving signals driving the memory device to communicate a respective one of the bit patterns to the controller.

16. The method according to claim 11, wherein driving the memory device to communicate the predetermined sequence of bit patterns to the controller comprises driving the memory device to communicate the predetermined sequence of bit patterns to the controller by communicating exactly one driving signal to the memory device.

17. The method according to claim 11, wherein the sequence of bit patterns includes at least N−

1 bit patterns, N being a number of the external terminals, each of the at least N−

1 bit patterns including exactly one bit having a value selected from the group consisting of;

0, and 1,

the method comprising driving the memory device to communicate the sequence to the controller.

18. An apparatus for use with a memory device, the apparatus comprising:

a memory controller, comprising;

a switching unit; and

a processor, configured to;

drive the memory device to communicate a predetermined sequence of bit patterns to the controller, and

in response to the sequence of bit patterns, set a bus bit order of the controller by controlling the switching unit.

19. The apparatus of claim 18, wherein the switching unit is configured to preserve connections between internal terminals of the memory controller and external terminals of the memory controller, following a powering-down of the controller.

20. The apparatus according to claim 18, wherein the processor is configured to:

communicate a reset command to the memory device; and

following the communication of the reset command and before beginning regular communication with the memory device, by communicating one or more driving signals to the memory device, drive the memory device to communicate the predetermined sequence of bit patterns to the controller.