BIT CELL WITH SHARED BIT LINE

• US 20160372518A1
• Filed: 06/19/2015
• Published: 12/22/2016
• Est. Priority Date: 06/19/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Li, Xia, Zhu, Xiaochun, Lu, Yu
• Granted Patent: US 10,008,537 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 MRAM devices H10B61/00

Abstract

A complementary bit cell includes a first magnetic tunnel junction (MTJ) device having a free layer coupled to a first access transistor and having a pinned layer coupled to a bit line. The complementary bit cell also includes a second MTJ device having a free layer coupled to the same bit line and having a pinned layer coupled to a second access transistor.

Claims

1. An apparatus comprising:

a first magnetic tunnel junction (MTJ) device having a free layer coupled to a first access transistor and having a pinned layer coupled to a bit line; and

a second MTJ device having a free layer coupled to the same bit line and having a pinned layer coupled to a second access transistor, the first MTJ device and the second MTJ device included in a complementary bit cell.

2. The apparatus of claim 1, wherein the complementary bit cell is included in a spin-transfer torque magnetic random access memory (STT-MRAM) device.

3. The apparatus of claim 1, further comprising:

a first source line coupled to the first access transistor; and

a second source line coupled to the second access transistor.

4. The apparatus of claim 1, wherein the first access transistor and the second access transistor are n-type metal oxide semiconductor (NMOS) transistors.

5. The apparatus of claim 1, further comprising an array of complementary bit cells, each complementary bit cell in the array of complementary bit cells including two MTJ devices coupled to a common bit line.

6. The apparatus of claim 5, wherein the complementary bit cell is included in the array of complementary bit cells.

7. The apparatus of claim 1, wherein the first MTJ device and the second MTJ device are configured to be programmed concurrently.

8. The apparatus of claim 1, further comprising a sensing amplifier configured to concurrently sense a data value of the first MTJ device and a data value of the second MTJ device.

9. The apparatus of claim 1, wherein the first MTJ device and the second MTJ device are located in different layers of the complementary bit cell.

10. The apparatus of claim 1, wherein the complementary bit cell is integrated into a mobile phone, a communications device, a personal digital assistant (PDA), a tablet, a navigation device, a music player, a video player, or an entertainment unit.

11. A method for forming a complementary bit cell, the method comprising:

coupling a free layer of a first magnetic tunnel junction (MTJ) device to a first access transistor using manufacturing equipment and coupling a pinned layer of the first MTJ device to a bit line using the manufacturing equipment; and

coupling a free layer of a second MTJ device to the same bit line using the manufacturing equipment and coupling a pinned layer of the second MTJ device to a second access transistor using the manufacturing equipment.

12. The method of claim 11, wherein the complementary bit cell is included in a spin-transfer torque magnetic random access memory (STT-MRAM) device.

13. The method of claim 11, further comprising:

coupling a first source line to the first access transistor using the manufacturing equipment; and

coupling a second source line to the second access transistor using the manufacturing equipment.

14. The method of claim 11, wherein the first access transistor and the second access transistor are n-type metal oxide semiconductor (NMOS) transistors.

15. The method of claim 11, wherein the first MTJ device and the second MTJ device are configured to be programmed concurrently.

16. The method of claim 11, wherein the first MTJ device and the second MTJ device are located in different layers of the complementary bit cell.

17. The method of claim 11, further comprising forming an array of complementary bit cells, each complementary bit cell in the array of complementary bit cells including two MTJ devices coupled to a common bit line.

18. The method of claim 17, wherein the complementary bit cell is included in the array of complementary bit cells.

19. A non-transitory computer-readable medium comprising data for enabling fabrication equipment to form a complementary bit cell, the data, when used by the fabrication equipment, causes the fabrication equipment to:

couple of a free layer of a first magnetic tunnel junction (MTJ) device to a first access transistor and couple of a pinned layer of the first MTJ device to a bit line; and

couple of a free layer of a second MTJ device to the bit line and couple of a pinned layer of the second MTJ device to a second access transistor.

20. The non-transitory computer-readable medium of claim 19, wherein the complementary bit cell is included in a spin-transfer torque magnetic random access memory (STT-MRAM) device.

21. The non-transitory computer-readable medium of claim 19, wherein the data further causes the fabrication equipment to:

couple of a first source line to the first access transistor; and

couple of a second source line to the second access transistor.

22. The non-transitory computer-readable medium of claim 19, wherein the first access transistor and the second access transistor are n-type metal oxide semiconductor (NMOS) transistors.

23. The non-transitory computer-readable medium of claim 19, wherein the first MTJ device and the second MTJ device are configured to be programmed concurrently.

24. The non-transitory computer-readable medium of claim 19, wherein the first MTJ device and the second MTJ device are located in different layers of the complementary bit cell.

25. An apparatus comprising:

first means for storing a first data value, the first means for storing having a first free layer coupled to a first access transistor and having a first pinned layer coupled to a bit line; and

second means for storing a second data value, the second means for storing having a second free layer coupled to the same bit line and having a second pinned layer coupled to a second access transistor, the first means for storing and the second means for storing included in a complementary bit cell.

26. The apparatus of claim 25, wherein the complementary bit cell is included in a spin-transfer torque magnetic random access memory (STT-MRAM) device.

27. The apparatus of claim 25, wherein the first means for storing includes a first magnetic tunnel junction (MTJ) device, and wherein the second means for storing includes a second MTJ device.

28. The apparatus of claim 25, further comprising an array of complementary bit cells, wherein the first means for storing and the second means for storing are included in the array of complementary bit cells.

29. The apparatus of claim 25, wherein the first means for storing and the second means for storing are configured to be programmed concurrently.

30. The apparatus of claim 25, wherein the first means for storing and the second means for storing are located in different layers of the complementary bit cell.