TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS

• US 20160372542A9
• Filed: 07/12/2014
• Published: 12/22/2016
• Est. Priority Date: 07/19/2011
• Status: Active Application

• Current Assignee: Anup Bhalla, Jongoh Kim, Madhur Bobde, Yeeheng Lee, Yongping Ding
• Original Assignee: Anup Bhalla, Jongoh Kim, Madhur Bobde, Yeeheng Lee, Yongping Ding
• Inventors: Lee, Yeeheng, Bobde, Madhur, Ding, Yongping, Kim, Jongoh, Bhalla, Anup
• Application Number:
  US14/329,936
• Publication Number:
  US 20160013267A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

Claims

1. A semiconductor power device disposed in a semiconductor substrate, comprising an upper doped region formed on top of a lower doped region with a lower dopant concentration than the upper doped region, and having an active cell area and an edge termination area wherein:

the edge termination area comprises a plurality of termination trenches formed on said heavily doped region, lined with a dielectric layer and filled with a conductive material therein;

a plurality of buried guard rings formed as doped regions in said lightly doped region of said semiconductor substrate immediately below a bottom surface of all of the termination trenches; and

the plurality of termination trenches are disposed with a distance between two adjacent termination trenches wherein the distance is smaller near the active area and the distance is increased for the adjacent trenches disposed farther away from the active cell area.

2. The semiconductor power device of claim 1 wherein:

the plurality of buried guard rings formed as doped regions in said lightly doped region of said semiconductor substrate immediately below the bottom surface and also surrounding sidewalls of the termination trenches wherein the buried guard rings are disposed around alternate termination trenches with every two of said guard rings separated by a middle termination trench not surrounded by said doped region.

3. The semiconductor power device of claim 1 wherein:

the plurality of termination trenches are formed to have the distance between the adjacent trenches ranging from 1 to 5 microns between two adjacent termination trenches.

4. The semiconductor power device of claim 1 wherein:

the plurality of termination trenches are formed to have a depth opened into the semiconductor substrate ranging from 2 to 8 microns.

5. The semiconductor power device of claim 1 wherein:

the buried guard rings formed as doped regions in said semiconductor substrate having a dopant concentration ranging from 1e16 to 1e19.

6. The semiconductor power device of claim 1 wherein:

the edge termination has a width ranging from 70 to 250 microns to form between 5 to 25 termination trenches in the edge termination.

7. A semiconductor power device disposed in a semiconductor substrate, comprising a heavily doped region formed on top of a lightly doped region, and having an active cell area and an edge termination area wherein:

the edge termination area comprises a plurality of termination trenches formed on said heavily doped region, lined with a dielectric layer and filled with a conductive material therein; and

a plurality of buried guard rings formed as doped regions in said lightly doped region of said semiconductor substrate immediately below a bottom surface and surrounding a lower portion of the termination trenches.

8. The semiconductor power device of claim 7 wherein:

the plurality of termination trenches are formed to have a distance ranging from 1 to 5 microns between two adjacent termination trenches.

9. The semiconductor power device of claim 7 wherein:

the plurality of termination trenches are formed to have a depth opened into the semiconductor substrate ranging from 2 to 8 microns.

10. The semiconductor power device of claim 7 wherein:

the buried guard rings formed as doped regions in said semiconductor substrate having a dopant concentration ranging from 1e16 to 1e19.

11. The semiconductor power device of claim 7 wherein:

the edge termination has a width ranging from 70 to 250 microns to form between 5 to 25 termination trenches in the edge termination.

12. A method for manufacturing a semiconductor power device in a semiconductor substrate, comprising a heavily doped region formed on top of a lightly doped region, and having an active cell area and an edge termination area comprising:

opening a plurality of termination trenches on said heavily doped region in the edge termination area;

implanting a plurality of doped regions through the termination trenches to function as buried guard rings in said lightly doped region of said semiconductor substrate immediately adjacent to the termination trenches; and

filling said termination trenches with a conductive filler for electrically connecting to a source electrode of said semiconductor power device.

13. The method of claim 12 wherein:

the step of implanting a plurality of doped regions through the termination trenches further comprising a step of applying an implanting mask for selectively implanting the doped regions below selected termination trenches.

14. The method of claim 12 wherein:

the step of implanting a plurality of doped regions through the termination trenches further comprising a step of filling the termination trenches with a photoresist material followed by applying a mask to selectively expose the photoresist material in selected termination trenches to a photolithographic radiation then removing the mask and the photoresist material from the selected termination trenches followed by selectively implanting the doped regions below the selected termination trenches.

15. The method of claim 13 wherein:

the step of implanting a plurality of doped regions through the termination trenches further comprising a step of forming an etch stop layer in said termination trenches then filling the termination trenches with a dielectric material followed by applying a mask to selectively etch the dielectric material from in selected termination trenches followed by implanting the doped regions below the selected termination trenches.

16. The method of claim 12 wherein:

the step of opening a plurality of termination trenches in the edge termination area comprises a step of opening the plurality of termination trenches to have a distance ranging from 1 to 5 microns between two adjacent termination trenches.