High Voltage Vertical FPMOS Fets

• US 20160372558A1
• Filed: 06/18/2015
• Published: 12/22/2016
• Est. Priority Date: 06/18/2015
• Status: Abandoned Application

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: FUKUNAGA, Shunsuke
• Application Number:
  US14/743,333
• Publication Number:
  US 20160372558A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor power devices such as vertical FPMOS are described having a plurality of trenches formed at a top portion of a semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction. Each trench has sidewalls generally perpendicular to a longitudinal direction of the trench and extending downward from a top surface to a trench bottom. Gate electrodes and source electrodes are positioned in the trenches. Higher voltage resistance is achieved while increasing current by spacing the trenches and providing particular dopant levels to allow more even distribution of depletion layer regions across a power device during use.

Claims

1. A semiconductor power device disposed in a semiconductor substrate, comprising:

trenches having defined widths formed at defined intervals perpendicular to and across a top portion of the semiconductor substrate extending laterally across the substrate and extending into an epitaxial layer;

base regions located outside the trenches;

trench source electrodes inside the trenches; and

gate electrodes inside the trenches positioned between the trench source electrodes and the base regions, wherein

a ratio of the intervals between trenches and the widths of the trenches is from 1.0 to 2.5.

2. The semiconductor power device of claim 1, wherein a dopant concentration of the base regions is between 5×

10E16 to 5×

10E17 per cubic centimeter.

3. The semiconductor power device of claim 1, wherein the epitaxial layer has an N−

dopant concentration of between 1.2E16 to 1.8E16 N−

per cubic centimeter.

4. The semiconductor power device of claim 2, wherein the epitaxial layer has an N−

dopant concentration of between 1.2E16 to 1.8E16 N−

per cubic centimeter.

5. The semiconductor power device of claim 1, lacking a peripheral trench structure.

6. The semiconductor power device of claim 1, wherein the trench source electrodes are centered in the trenches, and extend mostly to the bottom of the trenches.

7. The semiconductor power device of claim 6, wherein the gate electrodes are between the trench source electrodes and the trench walls, and extend only partially into the trenches adjacent to the base regions.

8. The semiconductor power device of claim 7, wherein the base regions are at the top of the epitaxial layer and extend down as far as the gate electrodes

9. The semiconductor power device of claim 1, wherein the trench widths are approximately 1.5 microns, wherein approximately comprises+/−

20%.

10. The semiconductor power device of claim 9, wherein the spacing between trenches is approximately 1.7 microns.

11. The semiconductor power device of claim 1, having depletion regions along the trenches that expand uniformly with applied voltage.

12-20. -20. (canceled)